📄 adder8.rpt
字号:
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\study\eda\8weiquanjiaqi\adder8.rpt
adder8
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 0/ 48( 0%) 2/ 48( 4%) 3/16( 18%) 4/16( 25%) 0/16( 0%)
B: 8/ 96( 8%) 6/ 48( 12%) 0/ 48( 0%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\study\eda\8weiquanjiaqi\adder8.rpt
adder8
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
a4 : INPUT;
a5 : INPUT;
a6 : INPUT;
a7 : INPUT;
b0 : INPUT;
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
b4 : INPUT;
b5 : INPUT;
b6 : INPUT;
b7 : INPUT;
cin : INPUT;
-- Node name is 'cout'
-- Equation name is 'cout', type is output
cout = _LC2_B11;
-- Node name is 's0'
-- Equation name is 's0', type is output
s0 = _LC5_A19;
-- Node name is 's1'
-- Equation name is 's1', type is output
s1 = _LC2_A19;
-- Node name is 's2'
-- Equation name is 's2', type is output
s2 = _LC7_A19;
-- Node name is 's3'
-- Equation name is 's3', type is output
s3 = _LC1_A19;
-- Node name is 's4'
-- Equation name is 's4', type is output
s4 = _LC8_B11;
-- Node name is 's5'
-- Equation name is 's5', type is output
s5 = _LC4_B11;
-- Node name is 's6'
-- Equation name is 's6', type is output
s6 = _LC6_B11;
-- Node name is 's7'
-- Equation name is 's7', type is output
s7 = _LC1_B11;
-- Node name is '|f_adder:adder0_map|h_adder:u2|:61'
-- Equation name is '_LC5_A19', type is buried
_LC5_A19 = LCELL( _EQ001);
_EQ001 = !a0 & b0 & !cin
# a0 & !b0 & !cin
# !a0 & !b0 & cin
# a0 & b0 & cin;
-- Node name is '|f_adder:adder0_map|or2a:u3|:4'
-- Equation name is '_LC4_A19', type is buried
!_LC4_A19 = _LC4_A19~NOT;
_LC4_A19~NOT = LCELL( _EQ002);
_EQ002 = !a0 & !cin
# !a0 & !b0
# !b0 & !cin;
-- Node name is '|f_adder:adder1_map|h_adder:u2|:61'
-- Equation name is '_LC2_A19', type is buried
_LC2_A19 = LCELL( _EQ003);
_EQ003 = !a1 & b1 & !_LC4_A19
# a1 & !b1 & !_LC4_A19
# !a1 & !b1 & _LC4_A19
# a1 & b1 & _LC4_A19;
-- Node name is '|f_adder:adder1_map|or2a:u3|:4'
-- Equation name is '_LC6_A19', type is buried
!_LC6_A19 = _LC6_A19~NOT;
_LC6_A19~NOT = LCELL( _EQ004);
_EQ004 = !a1 & !b1
# !a1 & !_LC4_A19
# !b1 & !_LC4_A19;
-- Node name is '|f_adder:adder2_map|h_adder:u2|:61'
-- Equation name is '_LC7_A19', type is buried
_LC7_A19 = LCELL( _EQ005);
_EQ005 = !a2 & b2 & !_LC6_A19
# a2 & !b2 & !_LC6_A19
# !a2 & !b2 & _LC6_A19
# a2 & b2 & _LC6_A19;
-- Node name is '|f_adder:adder2_map|or2a:u3|:4'
-- Equation name is '_LC8_A19', type is buried
!_LC8_A19 = _LC8_A19~NOT;
_LC8_A19~NOT = LCELL( _EQ006);
_EQ006 = !a2 & !_LC6_A19
# !a2 & !b2
# !b2 & !_LC6_A19;
-- Node name is '|f_adder:adder3_map|h_adder:u2|:61'
-- Equation name is '_LC1_A19', type is buried
_LC1_A19 = LCELL( _EQ007);
_EQ007 = !a3 & b3 & !_LC8_A19
# a3 & !b3 & !_LC8_A19
# !a3 & !b3 & _LC8_A19
# a3 & b3 & _LC8_A19;
-- Node name is '|f_adder:adder3_map|or2a:u3|:4'
-- Equation name is '_LC3_A19', type is buried
!_LC3_A19 = _LC3_A19~NOT;
_LC3_A19~NOT = LCELL( _EQ008);
_EQ008 = !a3 & !b3
# !a3 & !_LC8_A19
# !b3 & !_LC8_A19;
-- Node name is '|f_adder:adder4_map|h_adder:u2|:61'
-- Equation name is '_LC8_B11', type is buried
_LC8_B11 = LCELL( _EQ009);
_EQ009 = !a4 & b4 & !_LC3_A19
# a4 & !b4 & !_LC3_A19
# !a4 & !b4 & _LC3_A19
# a4 & b4 & _LC3_A19;
-- Node name is '|f_adder:adder4_map|or2a:u3|:4'
-- Equation name is '_LC3_B11', type is buried
!_LC3_B11 = _LC3_B11~NOT;
_LC3_B11~NOT = LCELL( _EQ010);
_EQ010 = !a4 & !_LC3_A19
# !a4 & !b4
# !b4 & !_LC3_A19;
-- Node name is '|f_adder:adder5_map|h_adder:u2|:61'
-- Equation name is '_LC4_B11', type is buried
_LC4_B11 = LCELL( _EQ011);
_EQ011 = !a5 & b5 & !_LC3_B11
# a5 & !b5 & !_LC3_B11
# !a5 & !b5 & _LC3_B11
# a5 & b5 & _LC3_B11;
-- Node name is '|f_adder:adder5_map|or2a:u3|:4'
-- Equation name is '_LC5_B11', type is buried
!_LC5_B11 = _LC5_B11~NOT;
_LC5_B11~NOT = LCELL( _EQ012);
_EQ012 = !a5 & !b5
# !a5 & !_LC3_B11
# !b5 & !_LC3_B11;
-- Node name is '|f_adder:adder6_map|h_adder:u2|:61'
-- Equation name is '_LC6_B11', type is buried
_LC6_B11 = LCELL( _EQ013);
_EQ013 = !a6 & b6 & !_LC5_B11
# a6 & !b6 & !_LC5_B11
# !a6 & !b6 & _LC5_B11
# a6 & b6 & _LC5_B11;
-- Node name is '|f_adder:adder6_map|or2a:u3|:4'
-- Equation name is '_LC7_B11', type is buried
!_LC7_B11 = _LC7_B11~NOT;
_LC7_B11~NOT = LCELL( _EQ014);
_EQ014 = !a6 & !_LC5_B11
# !a6 & !b6
# !b6 & !_LC5_B11;
-- Node name is '|f_adder:adder7_map|h_adder:u2|:61'
-- Equation name is '_LC1_B11', type is buried
_LC1_B11 = LCELL( _EQ015);
_EQ015 = !a7 & b7 & !_LC7_B11
# a7 & !b7 & !_LC7_B11
# !a7 & !b7 & _LC7_B11
# a7 & b7 & _LC7_B11;
-- Node name is '|f_adder:adder7_map|or2a:u3|:4'
-- Equation name is '_LC2_B11', type is buried
_LC2_B11 = LCELL( _EQ016);
_EQ016 = b7 & _LC7_B11
# a7 & _LC7_B11
# a7 & b7;
Project Information f:\study\eda\8weiquanjiaqi\adder8.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,066K
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