shzzh.fit.qmsg

来自「利用数字电路知识」· QMSG 代码 · 共 29 行 · 第 1/5 页

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "1khz Global clock in PIN 29 " "Info: Automatically promoted signal \"1khz\" to use Global clock in PIN 29" {  } { { "xianshi.bdf" "" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/新建文件夹/shzzh/xianshi.bdf" { { 608 40 208 624 "1khz" "" } { 432 64 120 448 "1khz" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}