dds.hif

直接数字频率合成

fenpin:inst2|74161:inst2|f74161:sub
fenpin:inst2|74161:inst1|f74161:sub
fenpin:inst2|74161:inst|f74161:sub
fenpin:inst2|74161:inst4|f74161:sub
}
# end
# entity
74161
# case_insensitive
# source_file
..|..|..|..|..|..|altera|quartus50|libraries|others|maxplus2|74161.tdf
1107570978
6
# storage
db|dds.(20).cnf
db|dds.(20).cnf
# user_parameter {
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
A
B
C
CLK
CLRN
D
ENP
ENT
LDN
QC
QD
}
# include_file {
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|aglobal.inc
1114012420
}
# hierarchies {
fenpin:inst2|74161:inst3
}
# end
# entity
74161
# case_insensitive
# source_file
..|..|..|..|..|..|altera|quartus50|libraries|others|maxplus2|74161.tdf
1107570978
6
# storage
db|dds.(21).cnf
db|dds.(21).cnf
# user_parameter {
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
A
B
C
CLK
CLRN
D
ENP
ENT
LDN
RCO
}
# include_file {
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|aglobal.inc
1114012420
}
# hierarchies {
fenpin:inst2|74161:inst2
fenpin:inst2|74161:inst
fenpin:inst2|74161:inst4
}
# end
# entity
74161
# case_insensitive
# source_file
..|..|..|..|..|..|altera|quartus50|libraries|others|maxplus2|74161.tdf
1107570978
6
# storage
db|dds.(22).cnf
db|dds.(22).cnf
# user_parameter {
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
A
B
C
CLK
CLRN
D
ENP
ENT
LDN
QA
QB
RCO
}
# include_file {
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|aglobal.inc
1114012420
}
# hierarchies {
fenpin:inst2|74161:inst1
}
# end
# entity
74138
# case_insensitive
# source_file
..|..|..|..|..|..|altera|quartus50|libraries|others|maxplus2|74138.bdf
1107570360
23
# storage
db|dds.(23).cnf
db|dds.(23).cnf
# hierarchies {
xianshi:inst10|74138:inst11
}
# end
# entity
7447
# case_insensitive
# source_file
..|..|..|..|..|..|altera|quartus50|libraries|others|maxplus2|7447.bdf
1107574798
23
# storage
db|dds.(26).cnf
db|dds.(26).cnf
# hierarchies {
xianshi:inst10|7447:inst9
}
# end
# entity
74151
# case_insensitive
# source_file
..|..|..|..|..|..|altera|quartus50|libraries|others|maxplus2|74151.tdf
1107570578
6
# storage
db|dds.(30).cnf
db|dds.(30).cnf
# user_parameter {
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
A
B
C
D0
D1
D2
D3
D4
D5
D6
D7
GN
Y
}
# include_file {
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|aglobal.inc
1114012420
}
# hierarchies {
xianshi:inst10|74151:inst6
xianshi:inst10|74151:inst5
xianshi:inst10|74151:inst4
xianshi:inst10|74151:inst7
}
# end
# entity
f74151
# case_insensitive
# source_file
..|..|..|..|..|..|altera|quartus50|libraries|others|maxplus2|f74151.bdf
1107578534
23
# storage
db|dds.(32).cnf
db|dds.(32).cnf
# hierarchies {
xianshi:inst10|74151:inst6|f74151:sub
xianshi:inst10|74151:inst5|f74151:sub
xianshi:inst10|74151:inst4|f74151:sub
xianshi:inst10|74151:inst7|f74151:sub
}
# end
# entity
altsyncram
# case_insensitive
# source_file
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|dds.(33).cnf
db|dds.(33).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
10
PARAMETER_DEC
USR
WIDTHAD_A
12
PARAMETER_DEC
USR
NUMWORDS_A
4096
PARAMETER_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
sin.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_rop
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a10
address_a11
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
}
# include_file {
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
sin_rom:inst4|altsyncram:altsyncram_component
}
# end
# entity
7482
# case_insensitive
# source_file
..|..|..|..|..|..|altera|quartus50|libraries|others|maxplus2|7482.bdf
1107576638
23
# storage
db|dds.(36).cnf
db|dds.(36).cnf
# hierarchies {
qufanjiayi:inst19|7482:inst2
}
# end
# entity
qufanjiayi
# case_insensitive
# source_file
qufanjiayi.bdf
1143883932
23
# storage
db|dds.(34).cnf
db|dds.(34).cnf
# hierarchies {
qufanjiayi:inst19
}
# end
# entity
zong3
# case_insensitive
# source_file
zong3.bdf
1143887566
23
# storage
db|dds.(37).cnf
db|dds.(37).cnf
# hierarchies {
|
}
# end
# entity
twowave_rom
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
twowave_rom.vhd
1205977394
4
# storage
db|dds.(38).cnf
db|dds.(38).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
twowave_rom:inst14
}
# end
# entity
altsyncram
# case_insensitive
# source_file
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|dds.(39).cnf
db|dds.(39).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
10
PARAMETER_DEC
USR
WIDTHAD_A
11
PARAMETER_DEC
USR
NUMWORDS_A
2048
PARAMETER_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
twowave.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_o6q
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a10
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
}
# include_file {
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
..|..|..|..|..|..|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
twowave_rom:inst14|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_o6q
# case_insensitive
# source_file
db|altsyncram_o6q.tdf
1205977768
6
# storage
db|dds.(40).cnf
db|dds.(40).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_a10
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
}
# memory_file {
twowave.mif
1205976566
}
# hierarchies {
twowave_rom:inst14|altsyncram:altsyncram_component|altsyncram_o6q:auto_generated
}
# end
# entity
chooseadr
# case_insensitive
# source_file
chooseadr.bdf
1143883572
23
# storage
db|dds.(41).cnf
db|dds.(41).cnf
# hierarchies {
chooseadr:inst5
}
# end
# complete