dds.fit.qmsg

直接数字频率合成

{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.518 ns register register " "Info: Estimated most critical path is register to register delay of 1.518 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cepin:inst11\|74160:inst1\|7 1 REG LAB_X46_Y12 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X46_Y12; Fanout = 4; REG Node = 'cepin:inst11\|74160:inst1\|7'" {  } { { "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/" "" "" { cepin:inst11|74160:inst1|7 } "NODE_NAME" } "" } } { "74160.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74160.bdf" { { 304 1032 1096 384 "7" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.780 ns) + CELL(0.738 ns) 1.518 ns cepin:inst11\|74173:inst5\|8 2 REG LAB_X44_Y12 1 " "Info: 2: + IC(0.780 ns) + CELL(0.738 ns) = 1.518 ns; Loc. = LAB_X44_Y12; Fanout = 1; REG Node = 'cepin:inst11\|74173:inst5\|8'" {  } { { "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/" "" "1.518 ns" { cepin:inst11|74160:inst1|7 cepin:inst11|74173:inst5|8 } "NODE_NAME" } "" } } { "74173.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74173.bdf" { { 312 592 656 392 "8" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns 48.62 % " "Info: Total cell delay = 0.738 ns ( 48.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.780 ns 51.38 % " "Info: Total interconnect delay = 0.780 ns ( 51.38 % )" {  } {  } 0}  } { { "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/" "" "1.518 ns" { cepin:inst11|74160:inst1|7 cepin:inst11|74173:inst5|8 } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 2 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 2%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "2 " "Warning: The following 2 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "mode1 VCC " "Info: Pin mode1 has VCC driving its datain port" {  } { { "zong3.bdf" "" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/zong3.bdf" { { 776 16 192 792 "mode1" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "mode1" } } } } { "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/" "" "" { mode1 } "NODE_NAME" } "" } } { "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/dds.fld" "" { Floorplan "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/dds.fld" "" "" { mode1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "mode2 GND " "Info: Pin mode2 has GND driving its datain port" {  } { { "zong3.bdf" "" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/zong3.bdf" { { 800 16 192 816 "mode2" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "mode2" } } } } { "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/" "" "" { mode2 } "NODE_NAME" } "" } } { "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/dds.fld" "" { Floorplan "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/dds.fld" "" "" { mode2 } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 01 18:33:08 2006 " "Info: Processing ended: Sat Apr 01 18:33:08 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0}  } {  } 0}