dds.fit.qmsg

直接数字频率合成

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 01 18:33:02 2006 " "Info: Processing started: Sat Apr 01 18:33:02 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off dds -c dds " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off dds -c dds" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "dds EP1C12Q240C8 " "Info: Selected device EP1C12Q240C8 for design \"dds\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6Q240C8 " "Info: Device EP1C6Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "cpz Global clock in PIN 28 " "Info: Automatically promoted signal \"cpz\" to use Global clock in PIN 28" {  } { { "zong3.bdf" "" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/zong3.bdf" { { 664 16 184 680 "cpz" "" } { 88 8 56 104 "cpz" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "mo48:inst1\|74160:inst4\|8 Global clock " "Info: Automatically promoted some destinations of signal \"mo48:inst1\|74160:inst4\|8\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "daclk " "Info: Destination \"daclk\" may be non-global or may not use global clock" {  } { { "zong3.bdf" "" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/zong3.bdf" { { 816 16 192 832 "daclk" "" } { 216 632 680 232 "daclk" "" } } } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "mo48:inst1\|74160:inst4\|8 " "Info: Destination \"mo48:inst1\|74160:inst4\|8\" may be non-global or may not use global clock" {  } { { "74160.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74160.bdf" { { 544 1032 1096 624 "8" "" } } } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "mo48:inst1\|74160:inst\|9 " "Info: Destination \"mo48:inst1\|74160:inst\|9\" may be non-global or may not use global clock" {  } { { "74160.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "mo48:inst1\|inst9~20 " "Info: Destination \"mo48:inst1\|inst9~20\" may be non-global or may not use global clock" {  } { { "mo48.bdf" "" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/mo48.bdf" { { 16 264 328 96 "inst9" "" } } } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "mo48:inst1\|74160:inst4\|9 " "Info: Destination \"mo48:inst1\|74160:inst4\|9\" may be non-global or may not use global clock" {  } { { "74160.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } }  } 0}  } { { "74160.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74160.bdf" { { 544 1032 1096 624 "8" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "fenpin:inst2\|74161:inst3\|f74161:sub\|110 Global clock " "Info: Automatically promoted some destinations of signal \"fenpin:inst2\|74161:inst3\|f74161:sub\|110\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fenpin:inst2\|74161:inst3\|f74161:sub\|110 " "Info: Destination \"fenpin:inst2\|74161:inst3\|f74161:sub\|110\" may be non-global or may not use global clock" {  } { { "f74161.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/f74161.bdf" { { 752 640 704 832 "110" "" } } } }  } 0}  } { { "f74161.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/f74161.bdf" { { 752 640 704 832 "110" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "cepin:inst11\|inst Global clock " "Info: Automatically promoted some destinations of signal \"cepin:inst11\|inst\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cepin:inst11\|inst " "Info: Destination \"cepin:inst11\|inst\" may be non-global or may not use global clock" {  } { { "cepin.bdf" "" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/cepin.bdf" { { 211 184 248 291 "inst" "" } } } }  } 0}  } { { "cepin.bdf" "" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/cepin.bdf" { { 211 184 248 291 "inst" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "inst3 Global clock " "Info: Automatically promoted signal \"inst3\" to use Global clock" {  } { { "zong3.bdf" "" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/dds实验/复件 huahua/zong3.bdf" { { 608 304 368 688 "inst3" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "fenpin:inst2\|74161:inst1\|f74161:sub\|87 Global clock " "Info: Automatically promoted some destinations of signal \"fenpin:inst2\|74161:inst1\|f74161:sub\|87\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fenpin:inst2\|74161:inst1\|f74161:sub\|87 " "Info: Destination \"fenpin:inst2\|74161:inst1\|f74161:sub\|87\" may be non-global or may not use global clock" {  } { { "f74161.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/f74161.bdf" { { 336 640 704 416 "87" "" } } } }  } 0}  } { { "f74161.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/f74161.bdf" { { 336 640 704 416 "87" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}