dds.map.eqn

直接数字频率合成

AB2L2 = R7_6 & (AB2L1 & (W7_7) # !AB2L1 & W5_7) # !R7_6 & (AB2L1);


--R6_8 is kpzi:inst9|74160:inst8|8
--operation mode is normal

R6_8_lut_out = R6_7 & (R6L6 $ (!J1L2 & R6_8)) # !R6_7 & (!J1L2 & R6_8);
R6_8 = DFFEAS(R6_8_lut_out, T4_110, VCC, , , , , , );


--R4_8 is kpzi:inst9|74160:inst1|8
--operation mode is normal

R4_8_lut_out = R4_7 & (R4L7 $ (!J1L1 & R4_8)) # !R4_7 & (!J1L1 & R4_8);
R4_8 = DFFEAS(R4_8_lut_out, T4_110, VCC, , , , , , );


--R3_8 is kpzi:inst9|74160:inst|8
--operation mode is normal

R3_8_lut_out = R3_7 & (R3L6 $ (!J1L1 & R3_8)) # !R3_7 & (!J1L1 & R3_8);
R3_8 = DFFEAS(R3_8_lut_out, T4_110, VCC, , , , , , );


--AB2L3 is xianshi:inst10|74151:inst5|f74151:sub|81~41
--operation mode is normal

AB2L3 = R7_7 & (R7_6) # !R7_7 & (R7_6 & R4_8 # !R7_6 & (R3_8));


--R5_8 is kpzi:inst9|74160:inst2|8
--operation mode is normal

R5_8_lut_out = R5_7 & (R5L7 $ (!J1L2 & R5_8)) # !R5_7 & (!J1L2 & R5_8);
R5_8 = DFFEAS(R5_8_lut_out, T4_110, VCC, , , , , , );


--AB2L4 is xianshi:inst10|74151:inst5|f74151:sub|81~42
--operation mode is normal

AB2L4 = R7_7 & (AB2L3 & (R5_8) # !AB2L3 & R6_8) # !R7_7 & (AB2L3);


--AB2L5 is xianshi:inst10|74151:inst5|f74151:sub|81~43
--operation mode is normal

AB2L5 = R7_8 & AB2L2 # !R7_8 & (AB2L4);


--W5_8 is cepin:inst11|74173:inst6|8
--operation mode is normal

W5_8_lut_out = R9_7;
W5_8 = DFFEAS(W5_8_lut_out, !L1_inst, VCC, , , , , , );


--W6_8 is cepin:inst11|74173:inst7|8
--operation mode is normal

W6_8_lut_out = R01_7;
W6_8 = DFFEAS(W6_8_lut_out, !L1_inst, VCC, , , , , , );


--W4_8 is cepin:inst11|74173:inst5|8
--operation mode is normal

W4_8_lut_out = R8_7;
W4_8 = DFFEAS(W4_8_lut_out, !L1_inst, VCC, , , , , , );


--AB3L1 is xianshi:inst10|74151:inst6|f74151:sub|81~28
--operation mode is normal

AB3L1 = R7_6 & (R7_7) # !R7_6 & (R7_7 & W6_8 # !R7_7 & (W4_8));


--W7_8 is cepin:inst11|74173:inst8|8
--operation mode is normal

W7_8_lut_out = R11_7;
W7_8 = DFFEAS(W7_8_lut_out, !L1_inst, VCC, , , , , , );


--AB3L2 is xianshi:inst10|74151:inst6|f74151:sub|81~29
--operation mode is normal

AB3L2 = R7_6 & (AB3L1 & (W7_8) # !AB3L1 & W5_8) # !R7_6 & (AB3L1);


--R6_7 is kpzi:inst9|74160:inst8|7
--operation mode is normal

R6_7_lut_out = R6_7 & (J1L2 $ (R6_9 # !R6L6)) # !R6_7 & R6L6 & (!R6_9);
R6_7 = DFFEAS(R6_7_lut_out, T4_110, VCC, , , , , , );


--R4_7 is kpzi:inst9|74160:inst1|7
--operation mode is normal

R4_7_lut_out = R4_7 & (J1L1 $ (R4_9 # !R4L7)) # !R4_7 & R4L7 & (!R4_9);
R4_7 = DFFEAS(R4_7_lut_out, T4_110, VCC, , , , , , );


--R3_7 is kpzi:inst9|74160:inst|7
--operation mode is normal

R3_7_lut_out = R3_7 & (J1L1 $ (R3_9 # !R3L6)) # !R3_7 & R3L6 & (!R3_9);
R3_7 = DFFEAS(R3_7_lut_out, T4_110, VCC, , , , , , );


--AB3L3 is xianshi:inst10|74151:inst6|f74151:sub|81~30
--operation mode is normal

AB3L3 = R7_7 & (R7_6) # !R7_7 & (R7_6 & R4_7 # !R7_6 & (R3_7));


--R5_7 is kpzi:inst9|74160:inst2|7
--operation mode is normal

R5_7_lut_out = R5_7 & (J1L2 $ (R5_9 # !R5L7)) # !R5_7 & R5L7 & (!R5_9);
R5_7 = DFFEAS(R5_7_lut_out, T4_110, VCC, , , , , , );


--AB3L4 is xianshi:inst10|74151:inst6|f74151:sub|81~31
--operation mode is normal

AB3L4 = R7_7 & (AB3L3 & (R5_7) # !AB3L3 & R6_7) # !R7_7 & (AB3L3);


--AB3L5 is xianshi:inst10|74151:inst6|f74151:sub|81~32
--operation mode is normal

AB3L5 = R7_8 & AB3L2 # !R7_8 & (AB3L4);


--W5_6 is cepin:inst11|74173:inst6|6
--operation mode is normal

W5_6_lut_out = R9_9;
W5_6 = DFFEAS(W5_6_lut_out, !L1_inst, VCC, , , , , , );


--W6_6 is cepin:inst11|74173:inst7|6
--operation mode is normal

W6_6_lut_out = R01_9;
W6_6 = DFFEAS(W6_6_lut_out, !L1_inst, VCC, , , , , , );


--W4_6 is cepin:inst11|74173:inst5|6
--operation mode is normal

W4_6_lut_out = R8_9;
W4_6 = DFFEAS(W4_6_lut_out, !L1_inst, VCC, , , , , , );


--AB1L1 is xianshi:inst10|74151:inst4|f74151:sub|81~30
--operation mode is normal

AB1L1 = R7_6 & (R7_7) # !R7_6 & (R7_7 & W6_6 # !R7_7 & (W4_6));


--W7_6 is cepin:inst11|74173:inst8|6
--operation mode is normal

W7_6_lut_out = R11_9;
W7_6 = DFFEAS(W7_6_lut_out, !L1_inst, VCC, , , , , , );


--AB1L2 is xianshi:inst10|74151:inst4|f74151:sub|81~31
--operation mode is normal

AB1L2 = R7_6 & (AB1L1 & (W7_6) # !AB1L1 & W5_6) # !R7_6 & (AB1L1);


--R6_9 is kpzi:inst9|74160:inst8|9
--operation mode is normal

R6_9_lut_out = R6L5 # R6_8 & R6_7 & R6L6;
R6_9 = DFFEAS(R6_9_lut_out, T4_110, VCC, , , , , , );


--R4_9 is kpzi:inst9|74160:inst1|9
--operation mode is normal

R4_9_lut_out = R4L5 # R4_8 & R4_7 & R4L7;
R4_9 = DFFEAS(R4_9_lut_out, T4_110, VCC, , , , , , );


--R3_9 is kpzi:inst9|74160:inst|9
--operation mode is normal

R3_9_lut_out = R3L5 # R3_8 & R3_7 & R3L6;
R3_9 = DFFEAS(R3_9_lut_out, T4_110, VCC, , , , , , );


--AB1L3 is xianshi:inst10|74151:inst4|f74151:sub|81~32
--operation mode is normal

AB1L3 = R7_7 & (R7_6) # !R7_7 & (R7_6 & R4_9 # !R7_6 & (R3_9));


--R5_9 is kpzi:inst9|74160:inst2|9
--operation mode is normal

R5_9_lut_out = R5L5 # R5_8 & R5_7 & R5L7;
R5_9 = DFFEAS(R5_9_lut_out, T4_110, VCC, , , , , , );


--AB1L4 is xianshi:inst10|74151:inst4|f74151:sub|81~33
--operation mode is normal

AB1L4 = R7_7 & (AB1L3 & (R5_9) # !AB1L3 & R6_9) # !R7_7 & (AB1L3);


--AB1L5 is xianshi:inst10|74151:inst4|f74151:sub|81~34
--operation mode is normal

AB1L5 = R7_8 & AB1L2 # !R7_8 & (AB1L4);


--Y1_87 is xianshi:inst10|7447:inst9|87
--operation mode is normal

Y1_87 = AB2L5 & AB4L5 & AB3L5 # !AB2L5 & (!AB3L5 & !AB1L5);


--Y1L6 is xianshi:inst10|7447:inst9|86~131
--operation mode is normal

Y1L6 = AB3L5 & (AB4L5 # !AB2L5) # !AB3L5 & AB4L5 & !AB1L5 & !AB2L5;


--Y1_85 is xianshi:inst10|7447:inst9|85
--operation mode is normal

Y1_85 = AB4L5 # AB2L5 & (!AB3L5);


--Y1L4 is xianshi:inst10|7447:inst9|84~132
--operation mode is normal

Y1L4 = AB2L5 & (AB4L5 $ !AB3L5) # !AB2L5 & AB4L5 & !AB3L5;


--Y1_83 is xianshi:inst10|7447:inst9|83
--operation mode is normal

Y1_83 = AB2L5 & AB1L5 # !AB2L5 & (AB3L5 & !AB4L5);


--Y1L2 is xianshi:inst10|7447:inst9|82~144
--operation mode is normal

Y1L2 = AB3L5 & (AB1L5 # AB2L5 & !AB4L5) # !AB3L5 & (AB2L5 & AB4L5);


--Y1L1 is xianshi:inst10|7447:inst9|81~37
--operation mode is normal

Y1L1 = AB3L5 & (AB1L5 # AB2L5 & !AB4L5) # !AB3L5 & (AB2L5 & (!AB4L5) # !AB2L5 & !AB1L5 & AB4L5);


--V1_q_a[9] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[9]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
V1_q_a[9]_PORT_A_address = BUS(W1_9, W1_8, W1_7, W1_6, W2_9, W2_8, W2_7, W2_6, W3_9, W3_8, W3_7, W3_6);
V1_q_a[9]_PORT_A_address_reg = DFFE(V1_q_a[9]_PORT_A_address, V1_q_a[9]_clock_0, , , );
V1_q_a[9]_clock_0 = R2_8;
V1_q_a[9]_PORT_A_data_out = MEMORY(, , V1_q_a[9]_PORT_A_address_reg, , , , , , V1_q_a[9]_clock_0, , , , , );
V1_q_a[9]_PORT_A_data_out_reg = DFFE(V1_q_a[9]_PORT_A_data_out, V1_q_a[9]_clock_0, , , );
V1_q_a[9] = V1_q_a[9]_PORT_A_data_out_reg[0];


--V1_q_a[8] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[8]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
V1_q_a[8]_PORT_A_address = BUS(W1_9, W1_8, W1_7, W1_6, W2_9, W2_8, W2_7, W2_6, W3_9, W3_8, W3_7, W3_6);
V1_q_a[8]_PORT_A_address_reg = DFFE(V1_q_a[8]_PORT_A_address, V1_q_a[8]_clock_0, , , );
V1_q_a[8]_clock_0 = R2_8;
V1_q_a[8]_PORT_A_data_out = MEMORY(, , V1_q_a[8]_PORT_A_address_reg, , , , , , V1_q_a[8]_clock_0, , , , , );
V1_q_a[8]_PORT_A_data_out_reg = DFFE(V1_q_a[8]_PORT_A_data_out, V1_q_a[8]_clock_0, , , );
V1_q_a[8] = V1_q_a[8]_PORT_A_data_out_reg[0];


--V1_q_a[7] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
V1_q_a[7]_PORT_A_address = BUS(W1_9, W1_8, W1_7, W1_6, W2_9, W2_8, W2_7, W2_6, W3_9, W3_8, W3_7, W3_6);
V1_q_a[7]_PORT_A_address_reg = DFFE(V1_q_a[7]_PORT_A_address, V1_q_a[7]_clock_0, , , );
V1_q_a[7]_clock_0 = R2_8;
V1_q_a[7]_PORT_A_data_out = MEMORY(, , V1_q_a[7]_PORT_A_address_reg, , , , , , V1_q_a[7]_clock_0, , , , , );
V1_q_a[7]_PORT_A_data_out_reg = DFFE(V1_q_a[7]_PORT_A_data_out, V1_q_a[7]_clock_0, , , );
V1_q_a[7] = V1_q_a[7]_PORT_A_data_out_reg[0];


--V1_q_a[6] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
V1_q_a[6]_PORT_A_address = BUS(W1_9, W1_8, W1_7, W1_6, W2_9, W2_8, W2_7, W2_6, W3_9, W3_8, W3_7, W3_6);
V1_q_a[6]_PORT_A_address_reg = DFFE(V1_q_a[6]_PORT_A_address, V1_q_a[6]_clock_0, , , );
V1_q_a[6]_clock_0 = R2_8;
V1_q_a[6]_PORT_A_data_out = MEMORY(, , V1_q_a[6]_PORT_A_address_reg, , , , , , V1_q_a[6]_clock_0, , , , , );
V1_q_a[6]_PORT_A_data_out_reg = DFFE(V1_q_a[6]_PORT_A_data_out, V1_q_a[6]_clock_0, , , );
V1_q_a[6] = V1_q_a[6]_PORT_A_data_out_reg[0];


--V1_q_a[5] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
V1_q_a[5]_PORT_A_address = BUS(W1_9, W1_8, W1_7, W1_6, W2_9, W2_8, W2_7, W2_6, W3_9, W3_8, W3_7, W3_6);
V1_q_a[5]_PORT_A_address_reg = DFFE(V1_q_a[5]_PORT_A_address, V1_q_a[5]_clock_0, , , );
V1_q_a[5]_clock_0 = R2_8;
V1_q_a[5]_PORT_A_data_out = MEMORY(, , V1_q_a[5]_PORT_A_address_reg, , , , , , V1_q_a[5]_clock_0, , , , , );
V1_q_a[5]_PORT_A_data_out_reg = DFFE(V1_q_a[5]_PORT_A_data_out, V1_q_a[5]_clock_0, , , );
V1_q_a[5] = V1_q_a[5]_PORT_A_data_out_reg[0];


--V1_q_a[4] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
V1_q_a[4]_PORT_A_address = BUS(W1_9, W1_8, W1_7, W1_6, W2_9, W2_8, W2_7, W2_6, W3_9, W3_8, W3_7, W3_6);
V1_q_a[4]_PORT_A_address_reg = DFFE(V1_q_a[4]_PORT_A_address, V1_q_a[4]_clock_0, , , );
V1_q_a[4]_clock_0 = R2_8;
V1_q_a[4]_PORT_A_data_out = MEMORY(, , V1_q_a[4]_PORT_A_address_reg, , , , , , V1_q_a[4]_clock_0, , , , , );
V1_q_a[4]_PORT_A_data_out_reg = DFFE(V1_q_a[4]_PORT_A_data_out, V1_q_a[4]_clock_0, , , );
V1_q_a[4] = V1_q_a[4]_PORT_A_data_out_reg[0];


--V1_q_a[3] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
V1_q_a[3]_PORT_A_address = BUS(W1_9, W1_8, W1_7, W1_6, W2_9, W2_8, W2_7, W2_6, W3_9, W3_8, W3_7, W3_6);
V1_q_a[3]_PORT_A_address_reg = DFFE(V1_q_a[3]_PORT_A_address, V1_q_a[3]_clock_0, , , );
V1_q_a[3]_clock_0 = R2_8;
V1_q_a[3]_PORT_A_data_out = MEMORY(, , V1_q_a[3]_PORT_A_address_reg, , , , , , V1_q_a[3]_clock_0, , , , , );
V1_q_a[3]_PORT_A_data_out_reg = DFFE(V1_q_a[3]_PORT_A_data_out, V1_q_a[3]_clock_0, , , );
V1_q_a[3] = V1_q_a[3]_PORT_A_data_out_reg[0];


--V1_q_a[2] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
V1_q_a[2]_PORT_A_address = BUS(W1_9, W1_8, W1_7, W1_6, W2_9, W2_8, W2_7, W2_6, W3_9, W3_8, W3_7, W3_6);
V1_q_a[2]_PORT_A_address_reg = DFFE(V1_q_a[2]_PORT_A_address, V1_q_a[2]_clock_0, , , );
V1_q_a[2]_clock_0 = R2_8;
V1_q_a[2]_PORT_A_data_out = MEMORY(, , V1_q_a[2]_PORT_A_address_reg, , , , , , V1_q_a[2]_clock_0, , , , , );
V1_q_a[2]_PORT_A_data_out_reg = DFFE(V1_q_a[2]_PORT_A_data_out, V1_q_a[2]_clock_0, , , );
V1_q_a[2] = V1_q_a[2]_PORT_A_data_out_reg[0];


--V1_q_a[1] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
V1_q_a[1]_PORT_A_address = BUS(W1_9, W1_8, W1_7, W1_6, W2_9, W2_8, W2_7, W2_6, W3_9, W3_8, W3_7, W3_6);
V1_q_a[1]_PORT_A_address_reg = DFFE(V1_q_a[1]_PORT_A_address, V1_q_a[1]_clock_0, , , );
V1_q_a[1]_clock_0 = R2_8;
V1_q_a[1]_PORT_A_data_out = MEMORY(, , V1_q_a[1]_PORT_A_address_reg, , , , , , V1_q_a[1]_clock_0, , , , , );
V1_q_a[1]_PORT_A_data_out_reg = DFFE(V1_q_a[1]_PORT_A_data_out, V1_q_a[1]_clock_0, , , );
V1_q_a[1] = V1_q_a[1]_PORT_A_data_out_reg[0];


--V1_q_a[0] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
V1_q_a[0]_PORT_A_address = BUS(W1_9, W1_8, W1_7, W1_6, W2_9, W2_8, W2_7, W2_6, W3_9, W3_8, W3_7, W3_6);
V1_q_a[0]_PORT_A_address_reg = DFFE(V1_q_a[0]_PORT_A_address, V1_q_a[0]_clock_0, , , );
V1_q_a[0]_clock_0 = R2_8;
V1_q_a[0]_PORT_A_data_out = MEMORY(, , V1_q_a[0]_PORT_A_address_reg, , , , , , V1_q_a[0]_clock_0, , , , , );
V1_q_a[0]_PORT_A_data_out_reg = DFFE(V1_q_a[0]_PORT_A_data_out, V1_q_a[0]_clock_0, , , );
V1_q_a[0] = V1_q_a[0]_PORT_A_data_out_reg[0];


--R2_7 is mo48:inst1|74160:inst4|7
--operation mode is normal

R2_7_lut_out = R2_7 & (C1L1 $ (R2_9 # !R2L7)) # !R2_7 & R2L7 & (!R2_9);
R2_7 = DFFEAS(R2_7_lut_out, cpz, VCC, , , , , , );


--R1_6 is mo48:inst1|74160:inst|6
--operation mode is normal

R1_6_lut_out = !R1_6;
R1_6 = DFFEAS(R1_6_lut_out, cpz, VCC, , , , , , );


--R2_6 is mo48:inst1|74160:inst4|6
--operation mode is normal

R2_6_lut_out = !C1L1 & (R2_6 $ (R1_6 & R1_9));
R2_6 = DFFEAS(R2_6_lut_out, cpz, VCC, , , , , , );


--R1_9 is mo48:inst1|74160:inst|9
--operation mode is normal

R1_9_lut_out = R1_7 & R1_8 & (!R2_8);
R1_9 = DFFEAS(R1_9_lut_out, cpz, VCC, , R1_6, , , , );


--R1_7 is mo48:inst1|74160:inst|7
--operation mode is normal

R1_7_lut_out = !C1L1 & (R1_7 $ (!R1_9 & R1_6));
R1_7 = DFFEAS(R1_7_lut_out, cpz, VCC, , , , , , );


--R1_8 is mo48:inst1|74160:inst|8
--operation mode is normal

R1_8_lut_out = !R1_8;
R1_8 = DFFEAS(R1_8_lut_out, cpz, VCC, , C1L2, , , , );


--C1L1 is mo48:inst1|inst9~20
--operation mode is normal

C1L1 = R2_8 & R1_6 & R1_7 & R1_8;


--R2L7 is mo48:inst1|74160:inst4|50~24
--operation mode is normal

R2L7 = R1_6 & R2_6 & R1_9 & !C1L1;


--W1_9 is leijiaqi2:inst6|74173:inst3|9
--operation mode is normal

W1_9_lut_out = !W1_9;
W1_9 = DFFEAS(W1_9_lut_out, R2_8, VCC, , T6_9, , , , );


--Q3L5 is adderpprom:inst|7483:inst2|51~92
--operation mode is normal

Q3L5 = W3_8 & !T7_87 & (!T7_9 # !W3_9) # !W3_8 & (!T7_87 # !T7_9 # !W3_9);


--F1L1 is chooseadr:inst5|inst14~12
--operation mode is normal

F1L1 = W3_7 $ T7_99 $ W1_9 $ !Q3L5;


--W1_8 is leijiaqi2:inst6|74173:inst3|8
--operation mode is normal

W1_8_lut_out = W1_8 $ T6_87 $ (W1_9 & T6_9);
W1_8 = DFFEAS(W1_8_lut_out, R2_8, VCC, , , , , , );


--F1L3 is chooseadr:inst5|inst19~2
--operation mode is normal

F1L3 = W3_7 $ T7_99 $ Q3L5 $ !W1_8;


--W1_7 is leijiaqi2:inst6|74173:inst3|7
--operation mode is normal

W1_7_lut_out = W1_7 $ T6_99 $ (!Q4L1 & !T6L7);
W1_7 = DFFEAS(W1_7_lut_out, R2_8, VCC, , , , , , );


--F1L4 is chooseadr:inst5|inst24~2
--operation mode is normal

F1L4 = W3_7 $ T7_99 $ Q3L5 $ !W1_7;


--W1_6 is leijiaqi2:inst6|74173:inst3|6
--operation mode is normal

W1_6_lut_out = W1_6 $ T6_110 $ !Q4L2;
W1_6 = DFFEAS(W1_6_lut_out, R2_8, VCC, , , , , , );


--F1L5 is chooseadr:inst5|inst29~2
--operation mode is normal

F1L5 = W3_7 $ T7_99 $ Q3L5 $ !W1_6;


--W2_9 is leijiaqi2:inst6|74173:inst4|9
--operation mode is normal