adder12.vhd

来自「直接数字频率合成」· VHDL 代码 · 共 11 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder12b is
   port(a,b:in std_logic_vector(11 downto 0);
         s:out std_logic_vector(11downto 0));
end adder12b;
architecture behav of adder12b is
   begin
s<=a+b;
end behav;