dds.fit.eqn

直接数字频率合成

R3_6_lut_out = R3_6 & !ke1 & (!R3_8 # !R4_6) # !R3_6 & (ke1);
R3_6 = DFFEAS(R3_6_lut_out, GLOBAL(T4_110), VCC, , , , , , );


--AB4L3 is xianshi:inst10|74151:inst7|f74151:sub|81~40 at LC_X45_Y11_N4
--operation mode is normal

AB4L3 = R7_6 & (R4_6 # R7_7) # !R7_6 & (!R7_7 & R3_6);


--R5_6 is kpzi:inst9|74160:inst2|6 at LC_X45_Y10_N1
--operation mode is normal

R5_6_lut_out = R5L6 & (!R5_6) # !R5L6 & R5_6 & (!R6_6 # !R6_8);
R5_6 = DFFEAS(R5_6_lut_out, GLOBAL(T4_110), VCC, , , , , , );


--AB4L4 is xianshi:inst10|74151:inst7|f74151:sub|81~41 at LC_X45_Y11_N2
--operation mode is normal

AB4L4 = AB4L3 & (R5_6 # !R7_7) # !AB4L3 & R6_6 & R7_7;


--AB4L5 is xianshi:inst10|74151:inst7|f74151:sub|81~42 at LC_X45_Y11_N9
--operation mode is normal

AB4L5 = R7_8 & (AB4L2) # !R7_8 & AB4L4;


--W4_7 is cepin:inst11|74173:inst5|7 at LC_X45_Y12_N3
--operation mode is normal

W4_7_lut_out = R8_8;
W4_7 = DFFEAS(W4_7_lut_out, !GLOBAL(L1_inst), VCC, , , , , , );


--AB2L1 is xianshi:inst10|74151:inst5|f74151:sub|81~39 at LC_X45_Y12_N6
--operation mode is normal

W6_7_qfbk = W6_7;
AB2L1 = R7_7 & (R7_6 # W6_7_qfbk) # !R7_7 & !R7_6 & (W4_7);

--W6_7 is cepin:inst11|74173:inst7|7 at LC_X45_Y12_N6
--operation mode is normal

W6_7 = DFFEAS(AB2L1, !GLOBAL(L1_inst), VCC, , , R01_8, , , VCC);


--W7_7 is cepin:inst11|74173:inst8|7 at LC_X43_Y11_N0
--operation mode is normal

W7_7_lut_out = R11_8;
W7_7 = DFFEAS(W7_7_lut_out, !GLOBAL(L1_inst), VCC, , , , , , );


--AB2L2 is xianshi:inst10|74151:inst5|f74151:sub|81~40 at LC_X45_Y12_N5
--operation mode is normal

W5_7_qfbk = W5_7;
AB2L2 = AB2L1 & (W7_7 # !R7_6) # !AB2L1 & R7_6 & W5_7_qfbk;

--W5_7 is cepin:inst11|74173:inst6|7 at LC_X45_Y12_N5
--operation mode is normal

W5_7 = DFFEAS(AB2L2, !GLOBAL(L1_inst), VCC, , , R9_8, , , VCC);


--R6_8 is kpzi:inst9|74160:inst8|8 at LC_X45_Y10_N2
--operation mode is normal

R6_8_lut_out = J1L2 & R6_7 & (R6L6) # !J1L2 & (R6_8 $ (R6_7 & R6L6));
R6_8 = DFFEAS(R6_8_lut_out, GLOBAL(T4_110), VCC, , , , , , );


--R4_8 is kpzi:inst9|74160:inst1|8 at LC_X40_Y12_N4
--operation mode is normal

R4_8_lut_out = R4_7 & (R4L7 $ (R4_8 & !J1L1)) # !R4_7 & (R4_8 & !J1L1);
R4_8 = DFFEAS(R4_8_lut_out, GLOBAL(T4_110), VCC, , , , , , );


--R3_8 is kpzi:inst9|74160:inst|8 at LC_X39_Y13_N9
--operation mode is normal

R3_8_lut_out = R3_7 & (R3L6 $ (!J1L1 & R3_8)) # !R3_7 & !J1L1 & R3_8;
R3_8 = DFFEAS(R3_8_lut_out, GLOBAL(T4_110), VCC, , , , , , );


--AB2L3 is xianshi:inst10|74151:inst5|f74151:sub|81~41 at LC_X45_Y12_N1
--operation mode is normal

AB2L3 = R7_6 & (R7_7 # R4_8) # !R7_6 & R3_8 & !R7_7;


--R5_8 is kpzi:inst9|74160:inst2|8 at LC_X44_Y10_N7
--operation mode is normal

R5_8_lut_out = R5L7 & (R5_7 $ (R5_8 & !J1L2)) # !R5L7 & (R5_8 & !J1L2);
R5_8 = DFFEAS(R5_8_lut_out, GLOBAL(T4_110), VCC, , , , , , );


--AB2L4 is xianshi:inst10|74151:inst5|f74151:sub|81~42 at LC_X45_Y12_N2
--operation mode is normal

AB2L4 = R7_7 & (AB2L3 & R5_8 # !AB2L3 & (R6_8)) # !R7_7 & (AB2L3);


--AB2L5 is xianshi:inst10|74151:inst5|f74151:sub|81~43 at LC_X45_Y12_N9
--operation mode is normal

AB2L5 = R7_8 & (AB2L2) # !R7_8 & AB2L4;


--W4_8 is cepin:inst11|74173:inst5|8 at LC_X44_Y12_N3
--operation mode is normal

W4_8_lut_out = GND;
W4_8 = DFFEAS(W4_8_lut_out, !GLOBAL(L1_inst), VCC, , , R8_7, , , VCC);


--AB3L1 is xianshi:inst10|74151:inst6|f74151:sub|81~28 at LC_X44_Y12_N2
--operation mode is normal

W6_8_qfbk = W6_8;
AB3L1 = R7_6 & R7_7 # !R7_6 & (R7_7 & W6_8_qfbk # !R7_7 & (W4_8));

--W6_8 is cepin:inst11|74173:inst7|8 at LC_X44_Y12_N2
--operation mode is normal

W6_8 = DFFEAS(AB3L1, !GLOBAL(L1_inst), VCC, , , R01_7, , , VCC);


--W7_8 is cepin:inst11|74173:inst8|8 at LC_X44_Y12_N0
--operation mode is normal

W7_8_lut_out = GND;
W7_8 = DFFEAS(W7_8_lut_out, !GLOBAL(L1_inst), VCC, , , R11_7, , , VCC);


--AB3L2 is xianshi:inst10|74151:inst6|f74151:sub|81~29 at LC_X44_Y12_N1
--operation mode is normal

W5_8_qfbk = W5_8;
AB3L2 = AB3L1 & (W7_8 # !R7_6) # !AB3L1 & R7_6 & W5_8_qfbk;

--W5_8 is cepin:inst11|74173:inst6|8 at LC_X44_Y12_N1
--operation mode is normal

W5_8 = DFFEAS(AB3L2, !GLOBAL(L1_inst), VCC, , , R9_7, , , VCC);


--R6_7 is kpzi:inst9|74160:inst8|7 at LC_X44_Y10_N0
--operation mode is normal

R6_7_lut_out = R6_9 & !J1L2 & (R6_7) # !R6_9 & (R6L6 $ (!J1L2 & R6_7));
R6_7 = DFFEAS(R6_7_lut_out, GLOBAL(T4_110), VCC, , , , , , );


--R4_7 is kpzi:inst9|74160:inst1|7 at LC_X40_Y12_N5
--operation mode is normal

R4_7_lut_out = R4_7 & (J1L1 $ (R4_9 # !R4L7)) # !R4_7 & R4L7 & !R4_9;
R4_7 = DFFEAS(R4_7_lut_out, GLOBAL(T4_110), VCC, , , , , , );


--R3_7 is kpzi:inst9|74160:inst|7 at LC_X39_Y12_N2
--operation mode is normal

R3_7_lut_out = R3_7 & (J1L1 $ (R3_9 # !R3L6)) # !R3_7 & R3L6 & !R3_9;
R3_7 = DFFEAS(R3_7_lut_out, GLOBAL(T4_110), VCC, , , , , , );


--AB3L3 is xianshi:inst10|74151:inst6|f74151:sub|81~30 at LC_X44_Y12_N5
--operation mode is normal

AB3L3 = R7_7 & (R7_6) # !R7_7 & (R7_6 & R4_7 # !R7_6 & (R3_7));


--R5_7 is kpzi:inst9|74160:inst2|7 at LC_X45_Y10_N5
--operation mode is normal

R5_7_lut_out = J1L2 & R5L7 & !R5_9 # !J1L2 & (R5_7 $ (R5L7 & !R5_9));
R5_7 = DFFEAS(R5_7_lut_out, GLOBAL(T4_110), VCC, , , , , , );


--AB3L4 is xianshi:inst10|74151:inst6|f74151:sub|81~31 at LC_X44_Y12_N6
--operation mode is normal

AB3L4 = R7_7 & (AB3L3 & R5_7 # !AB3L3 & (R6_7)) # !R7_7 & (AB3L3);


--AB3L5 is xianshi:inst10|74151:inst6|f74151:sub|81~32 at LC_X44_Y12_N4
--operation mode is normal

AB3L5 = R7_8 & (AB3L2) # !R7_8 & (AB3L4);


--W4_6 is cepin:inst11|74173:inst5|6 at LC_X44_Y11_N5
--operation mode is normal

W4_6_lut_out = GND;
W4_6 = DFFEAS(W4_6_lut_out, !GLOBAL(L1_inst), VCC, , , R8_9, , , VCC);


--AB1L1 is xianshi:inst10|74151:inst4|f74151:sub|81~30 at LC_X44_Y11_N0
--operation mode is normal

W6_6_qfbk = W6_6;
AB1L1 = R7_6 & R7_7 # !R7_6 & (R7_7 & W6_6_qfbk # !R7_7 & (W4_6));

--W6_6 is cepin:inst11|74173:inst7|6 at LC_X44_Y11_N0
--operation mode is normal

W6_6 = DFFEAS(AB1L1, !GLOBAL(L1_inst), VCC, , , R01_9, , , VCC);


--W7_6 is cepin:inst11|74173:inst8|6 at LC_X44_Y11_N3
--operation mode is normal

W7_6_lut_out = GND;
W7_6 = DFFEAS(W7_6_lut_out, !GLOBAL(L1_inst), VCC, , , R11_9, , , VCC);


--AB1L2 is xianshi:inst10|74151:inst4|f74151:sub|81~31 at LC_X44_Y11_N4
--operation mode is normal

W5_6_qfbk = W5_6;
AB1L2 = R7_6 & (AB1L1 & (W7_6) # !AB1L1 & W5_6_qfbk) # !R7_6 & AB1L1;

--W5_6 is cepin:inst11|74173:inst6|6 at LC_X44_Y11_N4
--operation mode is normal

W5_6 = DFFEAS(AB1L2, !GLOBAL(L1_inst), VCC, , , R9_9, , , VCC);


--R6_9 is kpzi:inst9|74160:inst8|9 at LC_X44_Y10_N3
--operation mode is normal

R6_9_lut_out = R6L5 # R6L6 & R6_8 & R6_7;
R6_9 = DFFEAS(R6_9_lut_out, GLOBAL(T4_110), VCC, , , , , , );


--R4_9 is kpzi:inst9|74160:inst1|9 at LC_X40_Y12_N7
--operation mode is normal

R4_9_lut_out = R4L5 # R4_7 & R4_8 & R4L7;
R4_9 = DFFEAS(R4_9_lut_out, GLOBAL(T4_110), VCC, , , , , , );


--R3_9 is kpzi:inst9|74160:inst|9 at LC_X40_Y12_N8
--operation mode is normal

R3_9_lut_out = R3L5 # R3_8 & R3_7 & R3L6;
R3_9 = DFFEAS(R3_9_lut_out, GLOBAL(T4_110), VCC, , , , , , );


--AB1L3 is xianshi:inst10|74151:inst4|f74151:sub|81~32 at LC_X44_Y10_N2
--operation mode is normal

AB1L3 = R7_7 & (R7_6) # !R7_7 & (R7_6 & R4_9 # !R7_6 & (R3_9));


--R5_9 is kpzi:inst9|74160:inst2|9 at LC_X45_Y10_N7
--operation mode is normal

R5_9_lut_out = R5L5 # R5_7 & R5L7 & R5_8;
R5_9 = DFFEAS(R5_9_lut_out, GLOBAL(T4_110), VCC, , , , , , );


--AB1L4 is xianshi:inst10|74151:inst4|f74151:sub|81~33 at LC_X44_Y10_N6
--operation mode is normal

AB1L4 = AB1L3 & (R5_9 # !R7_7) # !AB1L3 & R7_7 & (R6_9);


--AB1L5 is xianshi:inst10|74151:inst4|f74151:sub|81~34 at LC_X44_Y10_N9
--operation mode is normal

AB1L5 = R7_8 & (AB1L2) # !R7_8 & AB1L4;


--Y1_87 is xianshi:inst10|7447:inst9|87 at LC_X52_Y22_N6
--operation mode is normal

Y1_87 = AB2L5 & (AB3L5 & AB4L5) # !AB2L5 & !AB1L5 & !AB3L5;


--Y1L6 is xianshi:inst10|7447:inst9|86~131 at LC_X52_Y22_N2
--operation mode is normal

Y1L6 = AB2L5 & (AB3L5 & AB4L5) # !AB2L5 & (AB3L5 # !AB1L5 & AB4L5);


--Y1_85 is xianshi:inst10|7447:inst9|85 at LC_X52_Y22_N5
--operation mode is normal

Y1_85 = AB4L5 # AB2L5 & !AB3L5;


--Y1L4 is xianshi:inst10|7447:inst9|84~132 at LC_X52_Y22_N7
--operation mode is normal

Y1L4 = AB2L5 & (AB3L5 $ !AB4L5) # !AB2L5 & !AB3L5 & AB4L5;


--Y1_83 is xianshi:inst10|7447:inst9|83 at LC_X52_Y22_N8
--operation mode is normal

Y1_83 = AB2L5 & AB1L5 # !AB2L5 & (AB3L5 & !AB4L5);


--Y1L2 is xianshi:inst10|7447:inst9|82~144 at LC_X52_Y22_N9
--operation mode is normal

Y1L2 = AB3L5 & (AB1L5 # AB2L5 & !AB4L5) # !AB3L5 & (AB2L5 & AB4L5);


--Y1L1 is xianshi:inst10|7447:inst9|81~37 at LC_X52_Y22_N4
--operation mode is normal

Y1L1 = AB1L5 & (AB3L5 # AB2L5 & !AB4L5) # !AB1L5 & (AB2L5 & (!AB4L5) # !AB2L5 & !AB3L5 & AB4L5);


--V1_q_a[9] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[9] at M4K_X33_Y10
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
V1_q_a[9]_PORT_A_address = BUS(W1_9, W1_8, W1_7, W1_6, W2_9, W2_8, W2_7, W2_6, W3_9, W3_8, W3_7, W3_6);
V1_q_a[9]_PORT_A_address_reg = DFFE(V1_q_a[9]_PORT_A_address, V1_q_a[9]_clock_0, , , );
V1_q_a[9]_clock_0 = GLOBAL(R2_8);
V1_q_a[9]_PORT_A_data_out = MEMORY(, , V1_q_a[9]_PORT_A_address_reg, , , , , , V1_q_a[9]_clock_0, , , , , );
V1_q_a[9]_PORT_A_data_out_reg = DFFE(V1_q_a[9]_PORT_A_data_out, V1_q_a[9]_clock_0, , , );
V1_q_a[9] = V1_q_a[9]_PORT_A_data_out_reg[0];


--V1_q_a[8] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[8] at M4K_X33_Y11
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
V1_q_a[8]_PORT_A_address = BUS(W1_9, W1_8, W1_7, W1_6, W2_9, W2_8, W2_7, W2_6, W3_9, W3_8, W3_7, W3_6);
V1_q_a[8]_PORT_A_address_reg = DFFE(V1_q_a[8]_PORT_A_address, V1_q_a[8]_clock_0, , , );
V1_q_a[8]_clock_0 = GLOBAL(R2_8);
V1_q_a[8]_PORT_A_data_out = MEMORY(, , V1_q_a[8]_PORT_A_address_reg, , , , , , V1_q_a[8]_clock_0, , , , , );
V1_q_a[8]_PORT_A_data_out_reg = DFFE(V1_q_a[8]_PORT_A_data_out, V1_q_a[8]_clock_0, , , );
V1_q_a[8] = V1_q_a[8]_PORT_A_data_out_reg[0];


--V1_q_a[7] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[7] at M4K_X19_Y10
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
V1_q_a[7]_PORT_A_address = BUS(W1_9, W1_8, W1_7, W1_6, W2_9, W2_8, W2_7, W2_6, W3_9, W3_8, W3_7, W3_6);
V1_q_a[7]_PORT_A_address_reg = DFFE(V1_q_a[7]_PORT_A_address, V1_q_a[7]_clock_0, , , );
V1_q_a[7]_clock_0 = GLOBAL(R2_8);
V1_q_a[7]_PORT_A_data_out = MEMORY(, , V1_q_a[7]_PORT_A_address_reg, , , , , , V1_q_a[7]_clock_0, , , , , );
V1_q_a[7]_PORT_A_data_out_reg = DFFE(V1_q_a[7]_PORT_A_data_out, V1_q_a[7]_clock_0, , , );
V1_q_a[7] = V1_q_a[7]_PORT_A_data_out_reg[0];


--V1_q_a[6] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[6] at M4K_X33_Y14
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
V1_q_a[6]_PORT_A_address = BUS(W1_9, W1_8, W1_7, W1_6, W2_9, W2_8, W2_7, W2_6, W3_9, W3_8, W3_7, W3_6);
V1_q_a[6]_PORT_A_address_reg = DFFE(V1_q_a[6]_PORT_A_address, V1_q_a[6]_clock_0, , , );
V1_q_a[6]_clock_0 = GLOBAL(R2_8);
V1_q_a[6]_PORT_A_data_out = MEMORY(, , V1_q_a[6]_PORT_A_address_reg, , , , , , V1_q_a[6]_clock_0, , , , , );
V1_q_a[6]_PORT_A_data_out_reg = DFFE(V1_q_a[6]_PORT_A_data_out, V1_q_a[6]_clock_0, , , );
V1_q_a[6] = V1_q_a[6]_PORT_A_data_out_reg[0];


--V1_q_a[5] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[5] at M4K_X33_Y12
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
V1_q_a[5]_PORT_A_address = BUS(W1_9, W1_8, W1_7, W1_6, W2_9, W2_8, W2_7, W2_6, W3_9, W3_8, W3_7, W3_6);
V1_q_a[5]_PORT_A_address_reg = DFFE(V1_q_a[5]_PORT_A_address, V1_q_a[5]_clock_0, , , );
V1_q_a[5]_clock_0 = GLOBAL(R2_8);
V1_q_a[5]_PORT_A_data_out = MEMORY(, , V1_q_a[5]_PORT_A_address_reg, , , , , , V1_q_a[5]_clock_0, , , , , );
V1_q_a[5]_PORT_A_data_out_reg = DFFE(V1_q_a[5]_PORT_A_data_out, V1_q_a[5]_clock_0, , , );
V1_q_a[5] = V1_q_a[5]_PORT_A_data_out_reg[0];


--V1_q_a[4] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[4] at M4K_X33_Y13
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
V1_q_a[4]_PORT_A_address = BUS(W1_9, W1_8, W1_7, W1_6, W2_9, W2_8, W2_7, W2_6, W3_9, W3_8, W3_7, W3_6);
V1_q_a[4]_PORT_A_address_reg = DFFE(V1_q_a[4]_PORT_A_address, V1_q_a[4]_clock_0, , , );
V1_q_a[4]_clock_0 = GLOBAL(R2_8);
V1_q_a[4]_PORT_A_data_out = MEMORY(, , V1_q_a[4]_PORT_A_address_reg, , , , , , V1_q_a[4]_clock_0, , , , , );
V1_q_a[4]_PORT_A_data_out_reg = DFFE(V1_q_a[4]_PORT_A_data_out, V1_q_a[4]_clock_0, , , );
V1_q_a[4] = V1_q_a[4]_PORT_A_data_out_reg[0];


--V1_q_a[3] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[3] at M4K_X19_Y11
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
V1_q_a[3]_PORT_A_address = BUS(W1_9, W1_8, W1_7, W1_6, W2_9, W2_8, W2_7, W2_6, W3_9, W3_8, W3_7, W3_6);
V1_q_a[3]_PORT_A_address_reg = DFFE(V1_q_a[3]_PORT_A_address, V1_q_a[3]_clock_0, , , );
V1_q_a[3]_clock_0 = GLOBAL(R2_8);
V1_q_a[3]_PORT_A_data_out = MEMORY(, , V1_q_a[3]_PORT_A_address_reg, , , , , , V1_q_a[3]_clock_0, , , , , );
V1_q_a[3]_PORT_A_data_out_reg = DFFE(V1_q_a[3]_PORT_A_data_out, V1_q_a[3]_clock_0, , , );
V1_q_a[3] = V1_q_a[3]_PORT_A_data_out_reg[0];


--V1_q_a[2] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[2] at M4K_X19_Y13
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
V1_q_a[2]_PORT_A_address = BUS(W1_9, W1_8, W1_7, W1_6, W2_9, W2_8, W2_7, W2_6, W3_9, W3_8, W3_7, W3_6);
V1_q_a[2]_PORT_A_address_reg = DFFE(V1_q_a[2]_PORT_A_address, V1_q_a[2]_clock_0, , , );
V1_q_a[2]_clock_0 = GLOBAL(R2_8);
V1_q_a[2]_PORT_A_data_out = MEMORY(, , V1_q_a[2]_PORT_A_address_reg, , , , , , V1_q_a[2]_clock_0, , , , , );
V1_q_a[2]_PORT_A_data_out_reg = DFFE(V1_q_a[2]_PORT_A_data_out, V1_q_a[2]_clock_0, , , );
V1_q_a[2] = V1_q_a[2]_PORT_A_data_out_reg[0];


--V1_q_a[1] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[1] at M4K_X19_Y14
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10