dds.map.qmsg

直接数字频率合成

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cos_rom cos_rom:inst5 " "Info: Elaborating entity \"cos_rom\" for hierarchy \"cos_rom:inst5\"" {  } { { "zong1.bdf" "inst5" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/zong1.bdf" { { 272 544 704 352 "inst5" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../../altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../../altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram cos_rom:inst5\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"cos_rom:inst5\|altsyncram:altsyncram_component\"" {  } { { "cos_rom.vhd" "altsyncram_component" { Text "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/cos_rom.vhd" 80 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_mop.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_mop.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_mop " "Info: Found entity 1: altsyncram_mop" {  } { { "db/altsyncram_mop.tdf" "" { Text "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/altsyncram_mop.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_mop cos_rom:inst5\|altsyncram:altsyncram_component\|altsyncram_mop:auto_generated " "Info: Elaborating entity \"altsyncram_mop\" for hierarchy \"cos_rom:inst5\|altsyncram:altsyncram_component\|altsyncram_mop:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adderpp adderpp:inst " "Info: Elaborating entity \"adderpp\" for hierarchy \"adderpp:inst\"" {  } { { "zong1.bdf" "inst" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/zong1.bdf" { { 272 280 424 368 "inst" "" } } } }  } 0}
{ "Warning" "WGDFX_PRIMITIVE_IGNORED" "VCC inst3 " "Warning: Primitive \"VCC\" of instance \"inst3\" not used" {  } { { "adderpp.bdf" "" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/adderpp.bdf" { { 288 528 560 304 "inst3" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../../altera/quartus50/libraries/others/maxplus2/7483.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../../altera/quartus50/libraries/others/maxplus2/7483.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 7483 " "Info: Found entity 1: 7483" {  } { { "7483.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/7483.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7483 adderpp:inst\|7483:inst " "Info: Elaborating entity \"7483\" for hierarchy \"adderpp:inst\|7483:inst\"" {  } { { "adderpp.bdf" "inst" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/adderpp.bdf" { { 64 144 264 256 "inst" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "leijiaqi leijiaqi:inst3 " "Info: Elaborating entity \"leijiaqi\" for hierarchy \"leijiaqi:inst3\"" {  } { { "zong1.bdf" "inst3" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/zong1.bdf" { { 88 272 400 248 "inst3" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../../altera/quartus50/libraries/others/maxplus2/74173.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../../altera/quartus50/libraries/others/maxplus2/74173.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74173 " "Info: Found entity 1: 74173" {  } { { "74173.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74173.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74173 leijiaqi:inst3\|74173:inst3 " "Info: Elaborating entity \"74173\" for hierarchy \"leijiaqi:inst3\|74173:inst3\"" {  } { { "leijiaqi.bdf" "inst3" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/leijiaqi.bdf" { { 48 440 560 240 "inst3" "" } } } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "sin_rom.vhd 2 1 " "Info: Using design file sin_rom.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sin_rom-SYN " "Info: Found design unit 1: sin_rom-SYN" {  } { { "sin_rom.vhd" "" { Text "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/sin_rom.vhd" 49 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sin_rom " "Info: Found entity 1: sin_rom" {  } { { "sin_rom.vhd" "" { Text "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/sin_rom.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sin_rom sin_rom:inst4 " "Info: Elaborating entity \"sin_rom\" for hierarchy \"sin_rom:inst4\"" {  } { { "zong1.bdf" "inst4" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/zong1.bdf" { { 120 560 720 200 "inst4" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram sin_rom:inst4\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"sin_rom:inst4\|altsyncram:altsyncram_component\"" {  } { { "sin_rom.vhd" "altsyncram_component" { Text "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/sin_rom.vhd" 80 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_rop.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_rop.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_rop " "Info: Found entity 1: altsyncram_rop" {  } { { "db/altsyncram_rop.tdf" "" { Text "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/altsyncram_rop.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_rop sin_rom:inst4\|altsyncram:altsyncram_component\|altsyncram_rop:auto_generated " "Info: Elaborating entity \"altsyncram_rop\" for hierarchy \"sin_rom:inst4\|altsyncram:altsyncram_component\|altsyncram_rop:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "leijiaqi:inst3\|74173:inst5\|42 " "Warning: Converting TRI node \"leijiaqi:inst3\|74173:inst5\|42\" that feeds logic to a wire" {  } { { "74173.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74173.bdf" { { 160 720 768 192 "42" "" } } } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "leijiaqi:inst3\|74173:inst5\|43 " "Warning: Converting TRI node \"leijiaqi:inst3\|74173:inst5\|43\" that feeds logic to a wire" {  } { { "74173.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74173.bdf" { { 320 720 768 352 "43" "" } } } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "leijiaqi:inst3\|74173:inst5\|44 " "Warning: Converting TRI node \"leijiaqi:inst3\|74173:inst5\|44\" that feeds logic to a wire" {  } { { "74173.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74173.bdf" { { 480 720 768 512 "44" "" } } } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "leijiaqi:inst3\|74173:inst5\|45 " "Warning: Converting TRI node \"leijiaqi:inst3\|74173:inst5\|45\" that feeds logic to a wire" {  } { { "74173.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74173.bdf" { { 640 720 768 672 "45" "" } } } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "leijiaqi:inst3\|74173:inst4\|42 " "Warning: Converting TRI node \"leijiaqi:inst3\|74173:inst4\|42\" that feeds logic to a wire" {  } { { "74173.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74173.bdf" { { 160 720 768 192 "42" "" } } } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "leijiaqi:inst3\|74173:inst4\|43 " "Warning: Converting TRI node \"leijiaqi:inst3\|74173:inst4\|43\" that feeds logic to a wire" {  } { { "74173.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74173.bdf" { { 320 720 768 352 "43" "" } } } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "leijiaqi:inst3\|74173:inst4\|44 " "Warning: Converting TRI node \"leijiaqi:inst3\|74173:inst4\|44\" that feeds logic to a wire" {  } { { "74173.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74173.bdf" { { 480 720 768 512 "44" "" } } } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "leijiaqi:inst3\|74173:inst4\|45 " "Warning: Converting TRI node \"leijiaqi:inst3\|74173:inst4\|45\" that feeds logic to a wire" {  } { { "74173.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74173.bdf" { { 640 720 768 672 "45" "" } } } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "leijiaqi:inst3\|74173:inst3\|42 " "Warning: Converting TRI node \"leijiaqi:inst3\|74173:inst3\|42\" that feeds logic to a wire" {  } { { "74173.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74173.bdf" { { 160 720 768 192 "42" "" } } } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "leijiaqi:inst3\|74173:inst3\|43 " "Warning: Converting TRI node \"leijiaqi:inst3\|74173:inst3\|43\" that feeds logic to a wire" {  } { { "74173.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74173.bdf" { { 320 720 768 352 "43" "" } } } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "leijiaqi:inst3\|74173:inst3\|44 " "Warning: Converting TRI node \"leijiaqi:inst3\|74173:inst3\|44\" that feeds logic to a wire" {  } { { "74173.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74173.bdf" { { 480 720 768 512 "44" "" } } } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "leijiaqi:inst3\|74173:inst3\|45 " "Warning: Converting TRI node \"leijiaqi:inst3\|74173:inst3\|45\" that feeds logic to a wire" {  } { { "74173.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74173.bdf" { { 640 720 768 672 "45" "" } } } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "2 " "Info: Ignored 2 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "2 " "Info: Ignored 2 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "mode1 GND " "Warning: Pin \"mode1\" stuck at GND" {  } { { "zong1.bdf" "" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/zong1.bdf" { { 432 576 752 448 "mode1" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "mode2 GND " "Warning: Pin \"mode2\" stuck at GND" {  } { { "zong1.bdf" "" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/zong1.bdf" { { 456 576 752 472 "mode2" "" } } } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "93 " "Info: Implemented 93 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "9 " "Info: Implemented 9 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "23 " "Info: Implemented 23 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "41 " "Info: Implemented 41 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "20 " "Info: Implemented 20 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 18 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 01 10:59:55 2006 " "Info: Processing ended: Sat Apr 01 10:59:55 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}