dds.fit.qmsg

直接数字频率合成

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 01 10:59:56 2006 " "Info: Processing started: Sat Apr 01 10:59:56 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off dds -c dds " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off dds -c dds" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "dds EP1C12Q240C8 " "Info: Selected device EP1C12Q240C8 for design \"dds\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6Q240C8 " "Info: Device EP1C6Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "8 32 " "Info: No exact pin location assignment(s) for 8 pins of 32 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "p0 " "Info: Pin p0 not assigned to an exact location on the device" {  } { { "zong1.bdf" "" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/zong1.bdf" { { 448 72 240 464 "p0" "" } { 288 176 280 304 "p\[3..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "p0" } } } } { "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/" "" "" { p0 } "NODE_NAME" } "" } } { "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/dds.fld" "" { Floorplan "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/dds.fld" "" "" { p0 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "p1 " "Info: Pin p1 not assigned to an exact location on the device" {  } { { "zong1.bdf" "" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/zong1.bdf" { { 464 72 240 480 "p1" "" } { 288 176 280 304 "p\[3..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "p1" } } } } { "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/" "" "" { p1 } "NODE_NAME" } "" } } { "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/dds.fld" "" { Floorplan "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/dds.fld" "" "" { p1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "p2 " "Info: Pin p2 not assigned to an exact location on the device" {  } { { "zong1.bdf" "" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/zong1.bdf" { { 480 72 240 496 "p2" "" } { 288 176 280 304 "p\[3..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "p2" } } } } { "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/" "" "" { p2 } "NODE_NAME" } "" } } { "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/dds.fld" "" { Floorplan "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/dds.fld" "" "" { p2 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "p3 " "Info: Pin p3 not assigned to an exact location on the device" {  } { { "zong1.bdf" "" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/zong1.bdf" { { 496 72 240 512 "p3" "" } { 288 176 280 304 "p\[3..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "p3" } } } } { "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/" "" "" { p3 } "NODE_NAME" } "" } } { "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/dds.fld" "" { Floorplan "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/dds.fld" "" "" { p3 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "k1 " "Info: Pin k1 not assigned to an exact location on the device" {  } { { "zong1.bdf" "" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/zong1.bdf" { { 384 72 240 400 "k1" "" } { 120 232 272 136 "k1" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "k1" } } } } { "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/" "" "" { k1 } "NODE_NAME" } "" } } { "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/dds.fld" "" { Floorplan "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/dds.fld" "" "" { k1 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "k2 " "Info: Pin k2 not assigned to an exact location on the device" {  } { { "zong1.bdf" "" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/zong1.bdf" { { 400 72 240 416 "k2" "" } { 136 232 272 152 "k2" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "k2" } } } } { "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/" "" "" { k2 } "NODE_NAME" } "" } } { "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/dds.fld" "" { Floorplan "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/dds.fld" "" "" { k2 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "k3 " "Info: Pin k3 not assigned to an exact location on the device" {  } { { "zong1.bdf" "" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/zong1.bdf" { { 416 72 240 432 "k3" "" } { 152 232 272 168 "k3" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "k3" } } } } { "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/" "" "" { k3 } "NODE_NAME" } "" } } { "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/dds.fld" "" { Floorplan "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/dds.fld" "" "" { k3 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "k4 " "Info: Pin k4 not assigned to an exact location on the device" {  } { { "zong1.bdf" "" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/zong1.bdf" { { 432 72 240 448 "k4" "" } { 168 232 272 184 "k4" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "k4" } } } } { "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/dds_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/dds_cmp.qrpt" Compiler "dds" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/db/dds.quartus_db" { Floorplan "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/" "" "" { k4 } "NODE_NAME" } "" } } { "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/dds.fld" "" { Floorplan "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/dds.fld" "" "" { k4 } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "cpz Global clock in PIN 28 " "Info: Automatically promoted signal \"cpz\" to use Global clock in PIN 28" {  } { { "zong1.bdf" "" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/zong1.bdf" { { 368 72 240 384 "cpz" "" } { 120 24 72 136 "cpz" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "mo48:inst1\|74160:inst4\|8 Global clock " "Info: Automatically promoted some destinations of signal \"mo48:inst1\|74160:inst4\|8\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "daclk " "Info: Destination \"daclk\" may be non-global or may not use global clock" {  } { { "zong1.bdf" "" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/zong1.bdf" { { 480 576 752 496 "daclk" "" } { 392 408 456 408 "daclk" "" } } } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "mo48:inst1\|74160:inst4\|8 " "Info: Destination \"mo48:inst1\|74160:inst4\|8\" may be non-global or may not use global clock" {  } { { "74160.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74160.bdf" { { 544 1032 1096 624 "8" "" } } } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "mo48:inst1\|74160:inst\|9 " "Info: Destination \"mo48:inst1\|74160:inst\|9\" may be non-global or may not use global clock" {  } { { "74160.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "mo48:inst1\|inst9~20 " "Info: Destination \"mo48:inst1\|inst9~20\" may be non-global or may not use global clock" {  } { { "mo48.bdf" "" { Schematic "C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/mo48.bdf" { { 16 264 328 96 "inst9" "" } } } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "mo48:inst1\|74160:inst4\|9 " "Info: Destination \"mo48:inst1\|74160:inst4\|9\" may be non-global or may not use global clock" {  } { { "74160.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } }  } 0}  } { { "74160.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74160.bdf" { { 544 1032 1096 624 "8" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}