dds.tan.rpt

直接数字频率合成

; Worst-case tsu               ; N/A   ; None          ; 6.714 ns                         ; p3                                                                                 ; cos_rom:inst5|altsyncram:altsyncram_component|altsyncram_mop:auto_generated|ram_block1a2~porta_address_reg11 ;            ; cpz      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 16.059 ns                        ; sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[1] ; sin[1]                                                                                                       ; cpz        ;          ; 0            ;
; Worst-case th                ; N/A   ; None          ; 3.455 ns                         ; k2                                                                                 ; leijiaqi:inst3|74173:inst3|8                                                                                 ;            ; cpz      ; 0            ;
; Clock Setup: 'cpz'           ; N/A   ; None          ; 146.31 MHz ( period = 6.835 ns ) ; leijiaqi:inst3|74173:inst5|9                                                       ; cos_rom:inst5|altsyncram:altsyncram_component|altsyncram_mop:auto_generated|ram_block1a0~porta_address_reg10 ; cpz        ; cpz      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                                                                                    ;                                                                                                              ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C12Q240C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; cpz             ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'cpz'                                                                                                                                                                                                                                                                                                                                                                                                                      ;