dds.fit.eqn

直接数字频率合成

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--H2_8 is mo48:inst1|74160:inst4|8 at LC_X8_Y13_N7
--operation mode is normal

H2_8_lut_out = H2_8 & (C1L1 $ (!H2_7 # !H2L7)) # !H2_8 & (H2L7 & H2_7);
H2_8 = DFFEAS(H2_8_lut_out, GLOBAL(cpz), VCC, , , , , , );


--M1_q_a[9] is cos_rom:inst5|altsyncram:altsyncram_component|altsyncram_mop:auto_generated|q_a[9] at M4K_X19_Y10
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
M1_q_a[9]_PORT_A_address = BUS(J1_9, J1_8, J1_7, J1_6, J2_9, J2_8, J2_7, J2_6, G3L2, G3L3, G3_44, G3_45);
M1_q_a[9]_PORT_A_address_reg = DFFE(M1_q_a[9]_PORT_A_address, M1_q_a[9]_clock_0, , , );
M1_q_a[9]_clock_0 = GLOBAL(H2_8);
M1_q_a[9]_PORT_A_data_out = MEMORY(, , M1_q_a[9]_PORT_A_address_reg, , , , , , M1_q_a[9]_clock_0, , , , , );
M1_q_a[9]_PORT_A_data_out_reg = DFFE(M1_q_a[9]_PORT_A_data_out, M1_q_a[9]_clock_0, , , );
M1_q_a[9] = M1_q_a[9]_PORT_A_data_out_reg[0];


--M1_q_a[8] is cos_rom:inst5|altsyncram:altsyncram_component|altsyncram_mop:auto_generated|q_a[8] at M4K_X19_Y13
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
M1_q_a[8]_PORT_A_address = BUS(J1_9, J1_8, J1_7, J1_6, J2_9, J2_8, J2_7, J2_6, G3L2, G3L3, G3_44, G3_45);
M1_q_a[8]_PORT_A_address_reg = DFFE(M1_q_a[8]_PORT_A_address, M1_q_a[8]_clock_0, , , );
M1_q_a[8]_clock_0 = GLOBAL(H2_8);
M1_q_a[8]_PORT_A_data_out = MEMORY(, , M1_q_a[8]_PORT_A_address_reg, , , , , , M1_q_a[8]_clock_0, , , , , );
M1_q_a[8]_PORT_A_data_out_reg = DFFE(M1_q_a[8]_PORT_A_data_out, M1_q_a[8]_clock_0, , , );
M1_q_a[8] = M1_q_a[8]_PORT_A_data_out_reg[0];


--M1_q_a[7] is cos_rom:inst5|altsyncram:altsyncram_component|altsyncram_mop:auto_generated|q_a[7] at M4K_X19_Y15
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
M1_q_a[7]_PORT_A_address = BUS(J1_9, J1_8, J1_7, J1_6, J2_9, J2_8, J2_7, J2_6, G3L2, G3L3, G3_44, G3_45);
M1_q_a[7]_PORT_A_address_reg = DFFE(M1_q_a[7]_PORT_A_address, M1_q_a[7]_clock_0, , , );
M1_q_a[7]_clock_0 = GLOBAL(H2_8);
M1_q_a[7]_PORT_A_data_out = MEMORY(, , M1_q_a[7]_PORT_A_address_reg, , , , , , M1_q_a[7]_clock_0, , , , , );
M1_q_a[7]_PORT_A_data_out_reg = DFFE(M1_q_a[7]_PORT_A_data_out, M1_q_a[7]_clock_0, , , );
M1_q_a[7] = M1_q_a[7]_PORT_A_data_out_reg[0];


--M1_q_a[6] is cos_rom:inst5|altsyncram:altsyncram_component|altsyncram_mop:auto_generated|q_a[6] at M4K_X19_Y12
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
M1_q_a[6]_PORT_A_address = BUS(J1_9, J1_8, J1_7, J1_6, J2_9, J2_8, J2_7, J2_6, G3L2, G3L3, G3_44, G3_45);
M1_q_a[6]_PORT_A_address_reg = DFFE(M1_q_a[6]_PORT_A_address, M1_q_a[6]_clock_0, , , );
M1_q_a[6]_clock_0 = GLOBAL(H2_8);
M1_q_a[6]_PORT_A_data_out = MEMORY(, , M1_q_a[6]_PORT_A_address_reg, , , , , , M1_q_a[6]_clock_0, , , , , );
M1_q_a[6]_PORT_A_data_out_reg = DFFE(M1_q_a[6]_PORT_A_data_out, M1_q_a[6]_clock_0, , , );
M1_q_a[6] = M1_q_a[6]_PORT_A_data_out_reg[0];


--M1_q_a[5] is cos_rom:inst5|altsyncram:altsyncram_component|altsyncram_mop:auto_generated|q_a[5] at M4K_X19_Y16
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
M1_q_a[5]_PORT_A_address = BUS(J1_9, J1_8, J1_7, J1_6, J2_9, J2_8, J2_7, J2_6, G3L2, G3L3, G3_44, G3_45);
M1_q_a[5]_PORT_A_address_reg = DFFE(M1_q_a[5]_PORT_A_address, M1_q_a[5]_clock_0, , , );
M1_q_a[5]_clock_0 = GLOBAL(H2_8);
M1_q_a[5]_PORT_A_data_out = MEMORY(, , M1_q_a[5]_PORT_A_address_reg, , , , , , M1_q_a[5]_clock_0, , , , , );
M1_q_a[5]_PORT_A_data_out_reg = DFFE(M1_q_a[5]_PORT_A_data_out, M1_q_a[5]_clock_0, , , );
M1_q_a[5] = M1_q_a[5]_PORT_A_data_out_reg[0];


--M1_q_a[4] is cos_rom:inst5|altsyncram:altsyncram_component|altsyncram_mop:auto_generated|q_a[4] at M4K_X19_Y17
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
M1_q_a[4]_PORT_A_address = BUS(J1_9, J1_8, J1_7, J1_6, J2_9, J2_8, J2_7, J2_6, G3L2, G3L3, G3_44, G3_45);
M1_q_a[4]_PORT_A_address_reg = DFFE(M1_q_a[4]_PORT_A_address, M1_q_a[4]_clock_0, , , );
M1_q_a[4]_clock_0 = GLOBAL(H2_8);
M1_q_a[4]_PORT_A_data_out = MEMORY(, , M1_q_a[4]_PORT_A_address_reg, , , , , , M1_q_a[4]_clock_0, , , , , );
M1_q_a[4]_PORT_A_data_out_reg = DFFE(M1_q_a[4]_PORT_A_data_out, M1_q_a[4]_clock_0, , , );
M1_q_a[4] = M1_q_a[4]_PORT_A_data_out_reg[0];


--M1_q_a[3] is cos_rom:inst5|altsyncram:altsyncram_component|altsyncram_mop:auto_generated|q_a[3] at M4K_X19_Y14
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
M1_q_a[3]_PORT_A_address = BUS(J1_9, J1_8, J1_7, J1_6, J2_9, J2_8, J2_7, J2_6, G3L2, G3L3, G3_44, G3_45);
M1_q_a[3]_PORT_A_address_reg = DFFE(M1_q_a[3]_PORT_A_address, M1_q_a[3]_clock_0, , , );
M1_q_a[3]_clock_0 = GLOBAL(H2_8);
M1_q_a[3]_PORT_A_data_out = MEMORY(, , M1_q_a[3]_PORT_A_address_reg, , , , , , M1_q_a[3]_clock_0, , , , , );
M1_q_a[3]_PORT_A_data_out_reg = DFFE(M1_q_a[3]_PORT_A_data_out, M1_q_a[3]_clock_0, , , );
M1_q_a[3] = M1_q_a[3]_PORT_A_data_out_reg[0];


--M1_q_a[2] is cos_rom:inst5|altsyncram:altsyncram_component|altsyncram_mop:auto_generated|q_a[2] at M4K_X19_Y9
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
M1_q_a[2]_PORT_A_address = BUS(J1_9, J1_8, J1_7, J1_6, J2_9, J2_8, J2_7, J2_6, G3L2, G3L3, G3_44, G3_45);
M1_q_a[2]_PORT_A_address_reg = DFFE(M1_q_a[2]_PORT_A_address, M1_q_a[2]_clock_0, , , );
M1_q_a[2]_clock_0 = GLOBAL(H2_8);
M1_q_a[2]_PORT_A_data_out = MEMORY(, , M1_q_a[2]_PORT_A_address_reg, , , , , , M1_q_a[2]_clock_0, , , , , );
M1_q_a[2]_PORT_A_data_out_reg = DFFE(M1_q_a[2]_PORT_A_data_out, M1_q_a[2]_clock_0, , , );
M1_q_a[2] = M1_q_a[2]_PORT_A_data_out_reg[0];


--M1_q_a[1] is cos_rom:inst5|altsyncram:altsyncram_component|altsyncram_mop:auto_generated|q_a[1] at M4K_X19_Y11
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
M1_q_a[1]_PORT_A_address = BUS(J1_9, J1_8, J1_7, J1_6, J2_9, J2_8, J2_7, J2_6, G3L2, G3L3, G3_44, G3_45);
M1_q_a[1]_PORT_A_address_reg = DFFE(M1_q_a[1]_PORT_A_address, M1_q_a[1]_clock_0, , , );
M1_q_a[1]_clock_0 = GLOBAL(H2_8);
M1_q_a[1]_PORT_A_data_out = MEMORY(, , M1_q_a[1]_PORT_A_address_reg, , , , , , M1_q_a[1]_clock_0, , , , , );
M1_q_a[1]_PORT_A_data_out_reg = DFFE(M1_q_a[1]_PORT_A_data_out, M1_q_a[1]_clock_0, , , );
M1_q_a[1] = M1_q_a[1]_PORT_A_data_out_reg[0];


--M1_q_a[0] is cos_rom:inst5|altsyncram:altsyncram_component|altsyncram_mop:auto_generated|q_a[0] at M4K_X19_Y8
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
M1_q_a[0]_PORT_A_address = BUS(J1_9, J1_8, J1_7, J1_6, J2_9, J2_8, J2_7, J2_6, G3L2, G3L3, G3_44, G3_45);
M1_q_a[0]_PORT_A_address_reg = DFFE(M1_q_a[0]_PORT_A_address, M1_q_a[0]_clock_0, , , );
M1_q_a[0]_clock_0 = GLOBAL(H2_8);
M1_q_a[0]_PORT_A_data_out = MEMORY(, , M1_q_a[0]_PORT_A_address_reg, , , , , , M1_q_a[0]_clock_0, , , , , );
M1_q_a[0]_PORT_A_data_out_reg = DFFE(M1_q_a[0]_PORT_A_data_out, M1_q_a[0]_clock_0, , , );
M1_q_a[0] = M1_q_a[0]_PORT_A_data_out_reg[0];


--L1_q_a[9] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[9] at M4K_X33_Y8
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
L1_q_a[9]_PORT_A_address = BUS(J1_9, J1_8, J1_7, J1_6, J2_9, J2_8, J2_7, J2_6, J3_9, J3_8, J3_7, J3_6);
L1_q_a[9]_PORT_A_address_reg = DFFE(L1_q_a[9]_PORT_A_address, L1_q_a[9]_clock_0, , , );
L1_q_a[9]_clock_0 = GLOBAL(H2_8);
L1_q_a[9]_PORT_A_data_out = MEMORY(, , L1_q_a[9]_PORT_A_address_reg, , , , , , L1_q_a[9]_clock_0, , , , , );
L1_q_a[9]_PORT_A_data_out_reg = DFFE(L1_q_a[9]_PORT_A_data_out, L1_q_a[9]_clock_0, , , );
L1_q_a[9] = L1_q_a[9]_PORT_A_data_out_reg[0];


--L1_q_a[8] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[8] at M4K_X33_Y9
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
L1_q_a[8]_PORT_A_address = BUS(J1_9, J1_8, J1_7, J1_6, J2_9, J2_8, J2_7, J2_6, J3_9, J3_8, J3_7, J3_6);
L1_q_a[8]_PORT_A_address_reg = DFFE(L1_q_a[8]_PORT_A_address, L1_q_a[8]_clock_0, , , );
L1_q_a[8]_clock_0 = GLOBAL(H2_8);
L1_q_a[8]_PORT_A_data_out = MEMORY(, , L1_q_a[8]_PORT_A_address_reg, , , , , , L1_q_a[8]_clock_0, , , , , );
L1_q_a[8]_PORT_A_data_out_reg = DFFE(L1_q_a[8]_PORT_A_data_out, L1_q_a[8]_clock_0, , , );
L1_q_a[8] = L1_q_a[8]_PORT_A_data_out_reg[0];


--L1_q_a[7] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[7] at M4K_X33_Y10
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
L1_q_a[7]_PORT_A_address = BUS(J1_9, J1_8, J1_7, J1_6, J2_9, J2_8, J2_7, J2_6, J3_9, J3_8, J3_7, J3_6);
L1_q_a[7]_PORT_A_address_reg = DFFE(L1_q_a[7]_PORT_A_address, L1_q_a[7]_clock_0, , , );
L1_q_a[7]_clock_0 = GLOBAL(H2_8);
L1_q_a[7]_PORT_A_data_out = MEMORY(, , L1_q_a[7]_PORT_A_address_reg, , , , , , L1_q_a[7]_clock_0, , , , , );
L1_q_a[7]_PORT_A_data_out_reg = DFFE(L1_q_a[7]_PORT_A_data_out, L1_q_a[7]_clock_0, , , );
L1_q_a[7] = L1_q_a[7]_PORT_A_data_out_reg[0];


--L1_q_a[6] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[6] at M4K_X33_Y14
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
L1_q_a[6]_PORT_A_address = BUS(J1_9, J1_8, J1_7, J1_6, J2_9, J2_8, J2_7, J2_6, J3_9, J3_8, J3_7, J3_6);
L1_q_a[6]_PORT_A_address_reg = DFFE(L1_q_a[6]_PORT_A_address, L1_q_a[6]_clock_0, , , );
L1_q_a[6]_clock_0 = GLOBAL(H2_8);
L1_q_a[6]_PORT_A_data_out = MEMORY(, , L1_q_a[6]_PORT_A_address_reg, , , , , , L1_q_a[6]_clock_0, , , , , );
L1_q_a[6]_PORT_A_data_out_reg = DFFE(L1_q_a[6]_PORT_A_data_out, L1_q_a[6]_clock_0, , , );
L1_q_a[6] = L1_q_a[6]_PORT_A_data_out_reg[0];


--L1_q_a[5] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[5] at M4K_X33_Y17
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
L1_q_a[5]_PORT_A_address = BUS(J1_9, J1_8, J1_7, J1_6, J2_9, J2_8, J2_7, J2_6, J3_9, J3_8, J3_7, J3_6);
L1_q_a[5]_PORT_A_address_reg = DFFE(L1_q_a[5]_PORT_A_address, L1_q_a[5]_clock_0, , , );
L1_q_a[5]_clock_0 = GLOBAL(H2_8);
L1_q_a[5]_PORT_A_data_out = MEMORY(, , L1_q_a[5]_PORT_A_address_reg, , , , , , L1_q_a[5]_clock_0, , , , , );
L1_q_a[5]_PORT_A_data_out_reg = DFFE(L1_q_a[5]_PORT_A_data_out, L1_q_a[5]_clock_0, , , );
L1_q_a[5] = L1_q_a[5]_PORT_A_data_out_reg[0];


--L1_q_a[4] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[4] at M4K_X33_Y13
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
L1_q_a[4]_PORT_A_address = BUS(J1_9, J1_8, J1_7, J1_6, J2_9, J2_8, J2_7, J2_6, J3_9, J3_8, J3_7, J3_6);
L1_q_a[4]_PORT_A_address_reg = DFFE(L1_q_a[4]_PORT_A_address, L1_q_a[4]_clock_0, , , );
L1_q_a[4]_clock_0 = GLOBAL(H2_8);
L1_q_a[4]_PORT_A_data_out = MEMORY(, , L1_q_a[4]_PORT_A_address_reg, , , , , , L1_q_a[4]_clock_0, , , , , );
L1_q_a[4]_PORT_A_data_out_reg = DFFE(L1_q_a[4]_PORT_A_data_out, L1_q_a[4]_clock_0, , , );
L1_q_a[4] = L1_q_a[4]_PORT_A_data_out_reg[0];


--L1_q_a[3] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[3] at M4K_X33_Y11
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
L1_q_a[3]_PORT_A_address = BUS(J1_9, J1_8, J1_7, J1_6, J2_9, J2_8, J2_7, J2_6, J3_9, J3_8, J3_7, J3_6);
L1_q_a[3]_PORT_A_address_reg = DFFE(L1_q_a[3]_PORT_A_address, L1_q_a[3]_clock_0, , , );
L1_q_a[3]_clock_0 = GLOBAL(H2_8);
L1_q_a[3]_PORT_A_data_out = MEMORY(, , L1_q_a[3]_PORT_A_address_reg, , , , , , L1_q_a[3]_clock_0, , , , , );
L1_q_a[3]_PORT_A_data_out_reg = DFFE(L1_q_a[3]_PORT_A_data_out, L1_q_a[3]_clock_0, , , );
L1_q_a[3] = L1_q_a[3]_PORT_A_data_out_reg[0];


--L1_q_a[2] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[2] at M4K_X33_Y15
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
L1_q_a[2]_PORT_A_address = BUS(J1_9, J1_8, J1_7, J1_6, J2_9, J2_8, J2_7, J2_6, J3_9, J3_8, J3_7, J3_6);
L1_q_a[2]_PORT_A_address_reg = DFFE(L1_q_a[2]_PORT_A_address, L1_q_a[2]_clock_0, , , );
L1_q_a[2]_clock_0 = GLOBAL(H2_8);
L1_q_a[2]_PORT_A_data_out = MEMORY(, , L1_q_a[2]_PORT_A_address_reg, , , , , , L1_q_a[2]_clock_0, , , , , );
L1_q_a[2]_PORT_A_data_out_reg = DFFE(L1_q_a[2]_PORT_A_data_out, L1_q_a[2]_clock_0, , , );
L1_q_a[2] = L1_q_a[2]_PORT_A_data_out_reg[0];


--L1_q_a[1] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[1] at M4K_X33_Y12
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
L1_q_a[1]_PORT_A_address = BUS(J1_9, J1_8, J1_7, J1_6, J2_9, J2_8, J2_7, J2_6, J3_9, J3_8, J3_7, J3_6);
L1_q_a[1]_PORT_A_address_reg = DFFE(L1_q_a[1]_PORT_A_address, L1_q_a[1]_clock_0, , , );
L1_q_a[1]_clock_0 = GLOBAL(H2_8);
L1_q_a[1]_PORT_A_data_out = MEMORY(, , L1_q_a[1]_PORT_A_address_reg, , , , , , L1_q_a[1]_clock_0, , , , , );
L1_q_a[1]_PORT_A_data_out_reg = DFFE(L1_q_a[1]_PORT_A_data_out, L1_q_a[1]_clock_0, , , );
L1_q_a[1] = L1_q_a[1]_PORT_A_data_out_reg[0];


--L1_q_a[0] is sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated|q_a[0] at M4K_X33_Y16
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 4096, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
L1_q_a[0]_PORT_A_address = BUS(J1_9, J1_8, J1_7, J1_6, J2_9, J2_8, J2_7, J2_6, J3_9, J3_8, J3_7, J3_6);
L1_q_a[0]_PORT_A_address_reg = DFFE(L1_q_a[0]_PORT_A_address, L1_q_a[0]_clock_0, , , );
L1_q_a[0]_clock_0 = GLOBAL(H2_8);
L1_q_a[0]_PORT_A_data_out = MEMORY(, , L1_q_a[0]_PORT_A_address_reg, , , , , , L1_q_a[0]_clock_0, , , , , );
L1_q_a[0]_PORT_A_data_out_reg = DFFE(L1_q_a[0]_PORT_A_data_out, L1_q_a[0]_clock_0, , , );
L1_q_a[0] = L1_q_a[0]_PORT_A_data_out_reg[0];


--H2_7 is mo48:inst1|74160:inst4|7 at LC_X8_Y13_N3
--operation mode is normal

H2_7_lut_out = H2_9 & (!C1L1 & H2_7) # !H2_9 & (H2L7 $ (!C1L1 & H2_7));
H2_7 = DFFEAS(H2_7_lut_out, GLOBAL(cpz), VCC, , , , , , );


--H1_6 is mo48:inst1|74160:inst|6 at LC_X8_Y13_N6
--operation mode is normal

H1_6_lut_out = !H1_6;
H1_6 = DFFEAS(H1_6_lut_out, GLOBAL(cpz), VCC, , , , , , );


--H2_6 is mo48:inst1|74160:inst4|6 at LC_X8_Y13_N0
--operation mode is normal

H2_6_lut_out = !C1L1 & (H2_6 $ (H1_9 & H1_6));
H2_6 = DFFEAS(H2_6_lut_out, GLOBAL(cpz), VCC, , , , , , );


--H1_9 is mo48:inst1|74160:inst|9 at LC_X7_Y12_N5
--operation mode is normal

H1_9_lut_out = H1_8 & (!H2_8 & H1_7);
H1_9 = DFFEAS(H1_9_lut_out, GLOBAL(cpz), VCC, , H1_6, , , , );


--H1_7 is mo48:inst1|74160:inst|7 at LC_X8_Y13_N5
--operation mode is normal

H1_7_lut_out = !C1L1 & (H1_7 $ (!H1_9 & H1_6));
H1_7 = DFFEAS(H1_7_lut_out, GLOBAL(cpz), VCC, , , , , , );


--H1_8 is mo48:inst1|74160:inst|8 at LC_X8_Y13_N9
--operation mode is normal

H1_8_lut_out = !H1_8;
H1_8 = DFFEAS(H1_8_lut_out, GLOBAL(cpz), VCC, , C1L2, , , , );


--C1L1 is mo48:inst1|inst9~20 at LC_X8_Y13_N4
--operation mode is normal

C1L1 = H1_8 & H1_7 & H2_8 & H1_6;


--H2L7 is mo48:inst1|74160:inst4|50~24 at LC_X8_Y13_N8
--operation mode is normal

H2L7 = H1_9 & H2_6 & !C1L1 & H1_6;


--J1_9 is leijiaqi:inst3|74173:inst3|9 at LC_X24_Y13_N5
--operation mode is normal

J1_9_lut_out = !J1_9;
J1_9 = DFFEAS(J1_9_lut_out, GLOBAL(H2_8), VCC, , k1, , , , );


--J1_8 is leijiaqi:inst3|74173:inst3|8 at LC_X24_Y13_N6
--operation mode is normal

J1_8_lut_out = k2 $ J1_8 $ (k1 & J1_9);
J1_8 = DFFEAS(J1_8_lut_out, GLOBAL(H2_8), VCC, , , , , , );


--J1_7 is leijiaqi:inst3|74173:inst3|7 at LC_X24_Y13_N2
--operation mode is normal

J1_7_lut_out = G4L1 $ k3 $ !J1_7;
J1_7 = DFFEAS(J1_7_lut_out, GLOBAL(H2_8), VCC, , , , , , );


--J1_6 is leijiaqi:inst3|74173:inst3|6 at LC_X28_Y13_N4
--operation mode is normal

J1_6_lut_out = G4L2 $ J1_6 $ !k4;
J1_6 = DFFEAS(J1_6_lut_out, GLOBAL(H2_8), VCC, , , , , , );


--J2_9 is leijiaqi:inst3|74173:inst4|9 at LC_X28_Y13_N5
--operation mode is normal

J2_9_lut_out = !J2_9;
J2_9 = DFFEAS(J2_9_lut_out, GLOBAL(H2_8), VCC, , G4L3, , , , );