dds.map.rpt

直接数字频率合成

; ADDRESS_ACLR_A                     ; NONE           ; Untyped                              ;
; OUTDATA_ACLR_A                     ; NONE           ; Untyped                              ;
; WRCONTROL_ACLR_A                   ; NONE           ; Untyped                              ;
; INDATA_ACLR_A                      ; NONE           ; Untyped                              ;
; BYTEENA_ACLR_A                     ; NONE           ; Untyped                              ;
; WIDTH_B                            ; 1              ; Untyped                              ;
; WIDTHAD_B                          ; 1              ; Untyped                              ;
; NUMWORDS_B                         ; 1              ; Untyped                              ;
; INDATA_REG_B                       ; CLOCK1         ; Untyped                              ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1         ; Untyped                              ;
; RDCONTROL_REG_B                    ; CLOCK1         ; Untyped                              ;
; ADDRESS_REG_B                      ; CLOCK1         ; Untyped                              ;
; OUTDATA_REG_B                      ; UNREGISTERED   ; Untyped                              ;
; BYTEENA_REG_B                      ; CLOCK1         ; Untyped                              ;
; INDATA_ACLR_B                      ; NONE           ; Untyped                              ;
; WRCONTROL_ACLR_B                   ; NONE           ; Untyped                              ;
; ADDRESS_ACLR_B                     ; NONE           ; Untyped                              ;
; OUTDATA_ACLR_B                     ; NONE           ; Untyped                              ;
; RDCONTROL_ACLR_B                   ; NONE           ; Untyped                              ;
; BYTEENA_ACLR_B                     ; NONE           ; Untyped                              ;
; WIDTH_BYTEENA_A                    ; 1              ; Integer                              ;
; WIDTH_BYTEENA_B                    ; 1              ; Untyped                              ;
; RAM_BLOCK_TYPE                     ; AUTO           ; Untyped                              ;
; BYTE_SIZE                          ; 8              ; Untyped                              ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE      ; Untyped                              ;
; INIT_FILE                          ; sin.mif        ; Untyped                              ;
; INIT_FILE_LAYOUT                   ; PORT_A         ; Untyped                              ;
; MAXIMUM_DEPTH                      ; 0              ; Untyped                              ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL         ; Untyped                              ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL         ; Untyped                              ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL         ; Untyped                              ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL         ; Untyped                              ;
; DEVICE_FAMILY                      ; Cyclone        ; Untyped                              ;
; CBXI_PARAMETER                     ; altsyncram_rop ; Untyped                              ;
+------------------------------------+----------------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/Documents and Settings/Administrator.CF141A501F304D5/桌面/实验材料/EDAandDDS/ddsdds2/dds.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat Apr 01 10:59:52 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dds -c dds
Info: Found 1 design units, including 1 entities, in source file mo48.bdf
    Info: Found entity 1: mo48
Info: Found 1 design units, including 1 entities, in source file fenpin.bdf
    Info: Found entity 1: fenpin
Info: Found 1 design units, including 1 entities, in source file leijiaqi.bdf
    Info: Found entity 1: leijiaqi
Info: Found 1 design units, including 1 entities, in source file zong1.bdf
    Info: Found entity 1: zong1
Info: Found 1 design units, including 1 entities, in source file adderpp.bdf
    Info: Found entity 1: adderpp
Info: Found 1 design units, including 1 entities, in source file leijiaqi2.bdf
    Info: Found entity 1: leijiaqi2
Info: Found 1 design units, including 1 entities, in source file xianshi.bdf
    Info: Found entity 1: xianshi
Info: Found 1 design units, including 1 entities, in source file kpzi.bdf
    Info: Found entity 1: kpzi
Info: Found 1 design units, including 1 entities, in source file binarykpzi.bdf
    Info: Found entity 1: binarykpzi
Info: Found 1 design units, including 1 entities, in source file zong2.bdf
    Info: Found entity 1: zong2
Info: Found 1 design units, including 1 entities, in source file cepin.bdf
    Info: Found entity 1: cepin
Info: Found 1 design units, including 1 entities, in source file adderpprom.bdf
    Info: Found entity 1: adderpprom
Info: Found 1 design units, including 1 entities, in source file zong3.bdf
    Info: Found entity 1: zong3
Info: Found 1 design units, including 1 entities, in source file cepincepin.bdf
    Info: Found entity 1: cepincepin
Info: Elaborating entity "zong1" for the top level hierarchy
Warning: Found multiple base names
Info: Elaborating entity "mo48" for hierarchy "mo48:inst1"
Info: Found 1 design units, including 1 entities, in source file ../../../../../../altera/quartus50/libraries/others/maxplus2/74160.bdf
    Info: Found entity 1: 74160
Info: Elaborating entity "74160" for hierarchy "mo48:inst1|74160:inst4"
Info: Using design file cos_rom.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: cos_rom-SYN
    Info: Found entity 1: cos_rom
Info: Elaborating entity "cos_rom" for hierarchy "cos_rom:inst5"
Info: Found 1 design units, including 1 entities, in source file ../../../../../../altera/quartus50/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "cos_rom:inst5|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_mop.tdf
    Info: Found entity 1: altsyncram_mop
Info: Elaborating entity "altsyncram_mop" for hierarchy "cos_rom:inst5|altsyncram:altsyncram_component|altsyncram_mop:auto_generated"
Info: Elaborating entity "adderpp" for hierarchy "adderpp:inst"
Warning: Primitive "VCC" of instance "inst3" not used
Info: Found 1 design units, including 1 entities, in source file ../../../../../../altera/quartus50/libraries/others/maxplus2/7483.bdf
    Info: Found entity 1: 7483
Info: Elaborating entity "7483" for hierarchy "adderpp:inst|7483:inst"
Info: Elaborating entity "leijiaqi" for hierarchy "leijiaqi:inst3"
Info: Found 1 design units, including 1 entities, in source file ../../../../../../altera/quartus50/libraries/others/maxplus2/74173.bdf
    Info: Found entity 1: 74173
Info: Elaborating entity "74173" for hierarchy "leijiaqi:inst3|74173:inst3"
Info: Using design file sin_rom.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: sin_rom-SYN
    Info: Found entity 1: sin_rom
Info: Elaborating entity "sin_rom" for hierarchy "sin_rom:inst4"
Info: Elaborating entity "altsyncram" for hierarchy "sin_rom:inst4|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_rop.tdf
    Info: Found entity 1: altsyncram_rop
Info: Elaborating entity "altsyncram_rop" for hierarchy "sin_rom:inst4|altsyncram:altsyncram_component|altsyncram_rop:auto_generated"
Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN
    Warning: Converting TRI node "leijiaqi:inst3|74173:inst5|42" that feeds logic to a wire
    Warning: Converting TRI node "leijiaqi:inst3|74173:inst5|43" that feeds logic to a wire
    Warning: Converting TRI node "leijiaqi:inst3|74173:inst5|44" that feeds logic to a wire
    Warning: Converting TRI node "leijiaqi:inst3|74173:inst5|45" that feeds logic to a wire
    Warning: Converting TRI node "leijiaqi:inst3|74173:inst4|42" that feeds logic to a wire
    Warning: Converting TRI node "leijiaqi:inst3|74173:inst4|43" that feeds logic to a wire
    Warning: Converting TRI node "leijiaqi:inst3|74173:inst4|44" that feeds logic to a wire
    Warning: Converting TRI node "leijiaqi:inst3|74173:inst4|45" that feeds logic to a wire
    Warning: Converting TRI node "leijiaqi:inst3|74173:inst3|42" that feeds logic to a wire
    Warning: Converting TRI node "leijiaqi:inst3|74173:inst3|43" that feeds logic to a wire
    Warning: Converting TRI node "leijiaqi:inst3|74173:inst3|44" that feeds logic to a wire
    Warning: Converting TRI node "leijiaqi:inst3|74173:inst3|45" that feeds logic to a wire
Info: Ignored 2 buffer(s)
    Info: Ignored 2 SOFT buffer(s)
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "mode1" stuck at GND
    Warning: Pin "mode2" stuck at GND
Info: Implemented 93 device resources after synthesis - the final resource count might be different
    Info: Implemented 9 input pins
    Info: Implemented 23 output pins
    Info: Implemented 41 logic cells
    Info: Implemented 20 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 18 warnings
    Info: Processing ended: Sat Apr 01 10:59:55 2006
    Info: Elapsed time: 00:00:03