tbuf.vhd

一个有关于UART开发的自己的一个VHDL代码

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:43:08 03/14/2007 
-- Design Name: 
-- Module Name:    TBUF - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
---串口信号发送器
--说明：当信号输出许可时马上对输BUFF里的数据从tx输出
--每16个CLK输出一位数据，起始位为0停止位为1；做这些是为了让起和单片机的串口廉容
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TBUF is 
port( clk  :in std_logic;
     E_KEY :in std_logic_vector(5 downto 0);
        tx :out std_logic);
end TBUF;
 
architecture behav of TBUF is
type     states is (waiting_fiat_camd,send_start,send_data,send_stop);
signal   state:states:=waiting_fiat_camd;

SIGNAL   fiat_camd: std_logic;
SIGNAL   buff : std_logic_vector(7 downto 0);--8位数据缓冲器
SIGNAL   reset: std_logic;--复位信号
 
begin 
	 
	 process(clk,E_KEY)
	 begin
			if rising_edge(clk) then
				if E_KEY="000001" THEN
					fiat_camd<='1';
					reset<='0';
					buff<="11001100";
				else
					fiat_camd<='0';
					reset<='1';
				END IF;
			END IF;
	 end process;
				
	 

    process(clk,fiat_camd,reset)
      variable bit_count :integer range 0  to 7:=0;
      variable counter_16 :integer range 0  to 15:=0; 
     
   begin
       if reset='1'  then    
            --系统复位进入等侍态 tx为高电平;串口有空闲时都是高电平
			state<=waiting_fiat_camd; 
			bit_count:=0;
			counter_16:=0;tx<='1';
       elsif rising_edge(clk) then
         case state is
         	when  waiting_fiat_camd =>  --这在等发送命令的状态
             	if fiat_camd='1' then 
				    state<=send_start;
                	tx<='0'; --送出起始位
                	counter_16:=0;--计数器为0
              	end if;
         	when send_start  => --这是在发送起始位的状态
             	if  counter_16 >=15 then 
				    state<=send_data;
					counter_16:=0;--发送完了就进入移位态
                  	tx<=buff(bit_count);
                  	bit_count:=bit_count+1;                   
                else 
					   counter_16:=counter_16+1;--计数器没有到时间就+1一直到满了16个时钟
              	end if;
        	when send_data  =>--这是在移位输出态
                if  counter_16>=15 then 
					tx<=buff(bit_count);
					bit_count:=bit_count+1;
					counter_16:=0;
                    if bit_count=0 then 
						state<=send_stop;
					else null;
                    end if;
                 else 
						counter_16:=counter_16+1;
                   end if;
        	when send_stop   =>
                 if counter_16>=15 then 
						state<=waiting_fiat_camd;--如果停止位输出了16个时钟那么就进入下一次了送等
                 else 
						counter_16:=counter_16+1;
                 end if;
	        when others =>
	        end case;
	      end if;
	end process;
end behav;