top.vhd

一个有关于UART开发的自己的一个VHDL代码

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:37:39 03/14/2007 
-- Design Name: 
-- Module Name:    top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
    generic(frequency_division:integer :=325);  --50M DIVIDED TO 9600*16 单片机的串口通信协议 16 circuit 1 bit

    Port ( CLK : in  STD_LOGIC;
           E_KEY : in  STD_LOGIC_VECTOR (5 downto 0);
           D_RXD : in  STD_LOGIC;
           D_TXD : out  STD_LOGIC;
           E_7SEG : out  STD_LOGIC_VECTOR (3 downto 0);
           E_7SEG_ALL : out  STD_LOGIC;
           D_7SEG : out  STD_LOGIC_VECTOR (7 downto 0);
			  out_en : out  std_logic
			 );
end top;

architecture Behavioral of top is

component baud --声明波特发生器
        generic( N:integer:=325);
    PORT(
          clkin:in std_logic;
          clkout:out std_logic
         );
end component;

--component 	CTRL  is
--	port (
--			key      :   in    std_logic_vector(5 downto 0);
--			data     :   inout std_logic_vector(9 downto 0);
--			7seg     :   out   std_logic_vector(7 downto 0)
--			);
--end component;

component TBUF is
	port (
         clk  :in std_logic;
         E_KEY :in std_logic_vector(5 downto 0);
         tx :out std_logic
			);
end component;

component RBUF is
	port (
      clk,rx:in std_logic;
      out_en :out std_logic;
      buff:out std_logic_vector(7 downto 0);
		E_7SEG     : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		E_7SEG_ALL : OUT STD_LOGIC
			);
end component;

signal buf_clk :std_logic;

begin

	U1: baud    generic map(n=>frequency_division) --映射波特器分频系数
               	port map(clkin=>CLK,clkout=>buf_clk);
					
	U3: TBUF    port map(clk=>buf_clk,E_KEY=>E_KEY,tx=>D_TXD);
	U4: RBUF    port map(clk=>buf_clk,rx=>D_RXD,out_en=>out_en,buff=>D_7SEG,E_7SEG=>E_7SEG,E_7SEG_ALL=>E_7SEG_ALL);

end Behavioral;