writeram.v

来自「用SmartGen 生成一个2k*8 Dual Port RAM」· Verilog 代码 · 共 41 行

// writeram.v
module writeram(key,RI,clk,rst,Waddress,TI,Raddress,sendwr);

input         key;
input         clk;
input         RI;
input         TI;
output        sendwr;
output        rst;
output [10:0] Waddress;
output [10:0] Raddress;

parameter   wrcntbit=11;
parameter   rdcntbit=11;

reg [10:0]  Waddress;
reg [10:0]  Raddress;

reg         rst_reg;

reg [wrcntbit-1:0] wrcnt;
reg [rdcntbit-1:0] rdcnt;

wire      key_negedge;
reg       key_buff;

wire      rst_posedge,rst_negedge;
reg       rst_buff;

wire      RI_negedge;
reg       RI_buff;

wire        sendclk;
reg [15:0]  sendclkdiv;

wire        TI_posedge;
reg         TI_buff;

reg         rst1,rst2,rst3,rst4,rst5;

//下面产生写地址复位信号rst，同时该信号也是单片机复位信号，存储器的读写周期指示信号