lab_61.v

来自「this verilog file gives the user an abil」· Verilog 代码 · 共 11 行

module lab_61(SW[3:0], SW[7:4], SW[11:8], SW[15:12], HEX0[6:0],HEX1[6:0],HEX2[6:0],HEX3[6:0]);
input SW[3:0], SW[7:4], SW[11:8], SW[15:12];
output HEX0[6:0],HEX1[6:0],HEX2[6:0],HEX3[6:0];

assign HEX0[0] = SW3 | (SW2&SW0) | SW1 | (~SW2 & ~SW1 & ~SW0);
assign HEX0[1] = ~SW2 | (~SW0 & ~SW1 & ~SW3) | (~SW3 & SW0 & SW1);
assign HEX0[2] = ~SW1 | SW0 | (SW2 & SW1);
assign HEX0[3] = SW[3] | (SW[1] & ~SW[0]) | (~SW[3] & ~SW[2] & SW[1]) | (~SW[3] & ~SW[2] & ~SW[0]) | (SW[2] & ~SW[1] & SW[0]);
assign HEX0[4] = (~SW[2] & ~SW[1] & ~SW[0]) | (SW[1] & ~SW[0]);
assign HEX0[5] = (~SW[1] & ~SW[0]) | (SW[2] & ~SW[1]) | SW[3] | (SW[2] & ~SW[0]);
HEX0[6] = SW[3] | (SW[2] & ~SW[1]) | (SW[1] & ~SW[0]) | (~SW[3] & ~SW[2] & SW[1]);