myfifo_syn.v

fifo(1-6:1):using ip-code and rd wd interface

	wire  [4:0]   wire_dffpipe8_q;

	myfifo_dffpipe2   dffpipe8
	( 
	.clock(clock),
	.clrn(clrn),
	.d(d),
	.q(wire_dffpipe8_q));
	assign
		q = wire_dffpipe8_q;
endmodule //myfifo_alt_synch_pipe


//dffpipe DELAY=2 WIDTH=5 clock clrn d q ALTERA_INTERNAL_OPTIONS=X_ON_VIOLATION_OPTION=OFF
//VERSION_BEGIN 8.1 cbx_a_gray2bin 2008:05:19:09:32:04:SJ cbx_a_graycounter 2008:05:19:09:39:53:SJ cbx_altdpram 2008:05:19:10:27:12:SJ cbx_altsyncram 2008:08:26:11:57:11:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_dcfifo 2008:09:07:22:36:06:SJ cbx_fifo_common 2008:05:19:10:54:06:SJ cbx_flex10ke 2008:05:19:10:53:03:SJ cbx_lpm_add_sub 2008:05:19:10:49:01:SJ cbx_lpm_compare 2008:09:01:07:44:05:SJ cbx_lpm_counter 2008:05:19:10:42:20:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_lpm_mux 2008:05:19:10:30:36:SJ cbx_mgl 2008:08:08:15:16:18:SJ cbx_scfifo 2008:05:19:10:25:30:SJ cbx_stratix 2008:08:05:17:10:23:SJ cbx_stratixii 2008:08:07:13:54:47:SJ cbx_stratixiii 2008:07:11:13:32:02:SJ cbx_util_mgl 2008:07:18:09:58:54:SJ  VERSION_END


//dffpipe DELAY=2 WIDTH=5 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
//VERSION_BEGIN 8.1 cbx_mgl 2008:08:08:15:16:18:SJ cbx_stratixii 2008:08:07:13:54:47:SJ cbx_util_mgl 2008:07:18:09:58:54:SJ  VERSION_END

//synthesis_resources = reg 10 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF"} *)
module  myfifo_dffpipe3
	( 
	clock,
	clrn,
	d,
	q) /* synthesis synthesis_clearbox=1 */;
	input   clock;
	input   clrn;
	input   [4:0]  d;
	output   [4:0]  q;

	reg	[4:0]	dffe12a;
	reg	[4:0]	dffe13a;
	wire ena;
	wire prn;
	wire sclr;

	// synopsys translate_off
	initial
		dffe12a = 0;
	// synopsys translate_on
	always @ ( posedge clock or  negedge prn or  negedge clrn)
		if (prn == 1'b0) dffe12a <= {5{1'b1}};
		else if (clrn == 1'b0) dffe12a <= 5'b0;
		else if  (ena == 1'b1)   dffe12a <= (d & {5{(~ sclr)}});
	// synopsys translate_off
	initial
		dffe13a = 0;
	// synopsys translate_on
	always @ ( posedge clock or  negedge prn or  negedge clrn)
		if (prn == 1'b0) dffe13a <= {5{1'b1}};
		else if (clrn == 1'b0) dffe13a <= 5'b0;
		else if  (ena == 1'b1)   dffe13a <= (dffe12a & {5{(~ sclr)}});
	assign
		ena = 1'b1,
		prn = 1'b1,
		q = dffe13a,
		sclr = 1'b0;
endmodule //myfifo_dffpipe3

//synthesis_resources = reg 10 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"X_ON_VIOLATION_OPTION=OFF"} *)
module  myfifo_alt_synch_pipe1
	( 
	clock,
	clrn,
	d,
	q) /* synthesis synthesis_clearbox=1 */;
	input   clock;
	input   clrn;
	input   [4:0]  d;
	output   [4:0]  q;

	wire  [4:0]   wire_dffpipe11_q;

	myfifo_dffpipe3   dffpipe11
	( 
	.clock(clock),
	.clrn(clrn),
	.d(d),
	.q(wire_dffpipe11_q));
	assign
		q = wire_dffpipe11_q;
endmodule //myfifo_alt_synch_pipe1


//lpm_add_sub DEVICE_FAMILY="Cyclone II" LPM_DIRECTION="SUB" LPM_WIDTH=5 dataa datab result
//VERSION_BEGIN 8.1 cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2008:05:19:10:49:01:SJ cbx_mgl 2008:08:08:15:16:18:SJ cbx_stratix 2008:08:05:17:10:23:SJ cbx_stratixii 2008:08:07:13:54:47:SJ  VERSION_END


//lpm_compare DEVICE_FAMILY="Cyclone II" LPM_WIDTH=5 aeb dataa datab
//VERSION_BEGIN 8.1 cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2008:05:19:10:49:01:SJ cbx_lpm_compare 2008:09:01:07:44:05:SJ cbx_mgl 2008:08:08:15:16:18:SJ cbx_stratix 2008:08:05:17:10:23:SJ cbx_stratixii 2008:08:07:13:54:47:SJ  VERSION_END

//synthesis_resources = 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  myfifo_cmpr
	( 
	aeb,
	dataa,
	datab) /* synthesis synthesis_clearbox=1 */;
	output   aeb;
	input   [4:0]  dataa;
	input   [4:0]  datab;

	wire  [12:0]  data_wire;
	wire  eq_wire;
	wire  [0:0]  result_wire;

	assign
		aeb = eq_wire,
		data_wire = {datab[4], dataa[4], datab[3], dataa[3], datab[2], dataa[2], datab[1], dataa[1], datab[0], dataa[0], (data_wire[11] ^ data_wire[12]), ((data_wire[7] ^ data_wire[8]) | (data_wire[9] ^ data_wire[10])), ((data_wire[3] ^ data_wire[4]) | (data_wire[5] ^ data_wire[6]))},
		eq_wire = (~ result_wire),
		result_wire = ((data_wire[0] | data_wire[1]) | data_wire[2]);
endmodule //myfifo_cmpr

//synthesis_resources = lut 24 M4K 1 reg 60 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF;REMOVE_DUPLICATE_REGISTERS=OFF;suppress_da_rule_internal=d101;suppress_da_rule_internal=d102;suppress_da_rule_internal=s102;-name CUT ON -from rdptr_g -to ws_dgrp|dffpipe11|dffe12a;-name SDC_STATEMENT \"set_false_path -from *rdptr_g* -to *ws_dgrp|myfifo_dffpipe3:dffpipe11|dffe12a* \";-name CUT ON -from delayed_wrptr_g -to rs_dgwp|dffpipe8|dffe9a;-name SDC_STATEMENT \"set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|myfifo_dffpipe2:dffpipe8|dffe9a* \""} *)
module  myfifo_dcfifo
	( 
	aclr,
	data,
	q,
	rdclk,
	rdempty,
	rdreq,
	rdusedw,
	wrclk,
	wrfull,
	wrreq) /* synthesis synthesis_clearbox=1 */;
	input   aclr;
	input   [7:0]  data;
	output   [7:0]  q;
	input   rdclk;
	output   rdempty;
	input   rdreq;
	output   [3:0]  rdusedw;
	input   wrclk;
	output   wrfull;
	input   wrreq;

	wire  [4:0]   wire_rdptr_g_gray2bin_bin;
	wire  [4:0]   wire_rs_dgwp_gray2bin_bin;
	wire  [4:0]   wire_rdptr_g1p_q;
	wire  [4:0]   wire_wrptr_g1p_q;
	wire  [4:0]   wire_wrptr_gp_q;
	wire  [7:0]   wire_fifo_ram_q_b;
	reg	[4:0]	delayed_wrptr_g;
	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
	reg	p0addr;
	(* ALTERA_ATTRIBUTE = {"suppress_da_rule_internal=r105"} *)
	reg	[4:0]	rdptr_g;
	wire  [0:0]   wire_rdaclr_q;
	wire  [4:0]   wire_rs_brp_q;
	wire  [4:0]   wire_rs_bwp_q;
	wire  [4:0]   wire_rs_dgwp_q;
	wire  [4:0]   wire_ws_dgrp_q;
	wire	[4:0]	wire_rdusedw_sub_dataa;
	wire	[4:0]	wire_rdusedw_sub_datab;
	wire	[4:0]	wire_rdusedw_sub_result;
	wire  wire_rdempty_eq_comp_aeb;
	wire  wire_wrfull_eq_comp_aeb;
	wire  int_rdempty;
	wire  int_wrfull;
	wire  [3:0]  ram_address_a;
	wire  [3:0]  ram_address_b;
	wire  rdcnt_addr_ena;
	wire  valid_rdreq;
	wire  valid_wrreq;
	wire  [4:0]  wrptr_gs;

	myfifo_a_gray2bin   rdptr_g_gray2bin
	( 
	.bin(wire_rdptr_g_gray2bin_bin),
	.gray(rdptr_g[4:0]));
	myfifo_a_gray2bin   rs_dgwp_gray2bin
	( 
	.bin(wire_rs_dgwp_gray2bin_bin),
	.gray(wire_rs_dgwp_q[4:0]));
	myfifo_a_graycounter   rdptr_g1p
	( 
	.aclr((~ wire_rdaclr_q)),
	.clock(rdclk),
	.cnt_en(rdcnt_addr_ena),
	.q(wire_rdptr_g1p_q));
	myfifo_a_graycounter1   wrptr_g1p
	( 
	.aclr(aclr),
	.clock(wrclk),
	.cnt_en(valid_wrreq),
	.q(wire_wrptr_g1p_q));
	myfifo_a_graycounter2   wrptr_gp
	( 
	.aclr(aclr),
	.clock(wrclk),
	.cnt_en(valid_wrreq),
	.q(wire_wrptr_gp_q));
	myfifo_altsyncram   fifo_ram
	( 
	.aclr1(aclr),
	.address_a(ram_address_a),
	.address_b(ram_address_b),
	.addressstall_b((~ rdcnt_addr_ena)),
	.clock0(wrclk),
	.clock1(rdclk),
	.clocken1(valid_rdreq),
	.data_a(data),
	.q_b(wire_fifo_ram_q_b),
	.wren_a(valid_wrreq));
	// synopsys translate_off
	initial
		delayed_wrptr_g = 0;
	// synopsys translate_on
	always @ ( posedge wrclk or  posedge aclr)
		if (aclr == 1'b1) delayed_wrptr_g <= 5'b0;
		else  delayed_wrptr_g <= wire_wrptr_gp_q;
	// synopsys translate_off
	initial
		p0addr = 0;
	// synopsys translate_on
	always @ ( posedge rdclk or  negedge wire_rdaclr_q)
		if (wire_rdaclr_q == 1'b0) p0addr <= 1'b0;
		else  p0addr <= 1'b1;
	// synopsys translate_off
	initial
		rdptr_g = 0;
	// synopsys translate_on
	always @ ( posedge rdclk or  posedge aclr)
		if (aclr == 1'b1) rdptr_g <= 5'b0;
		else if  (valid_rdreq == 1'b1)   rdptr_g <= wire_rdptr_g1p_q;
	myfifo_dffpipe   rdaclr
	( 
	.clock((~ rdclk)),
	.clrn((~ aclr)),
	.d(1'b1),
	.q(wire_rdaclr_q));
	myfifo_dffpipe1   rs_brp
	( 
	.clock(rdclk),
	.clrn((~ aclr)),
	.d(wire_rdptr_g_gray2bin_bin),
	.q(wire_rs_brp_q));
	myfifo_dffpipe1   rs_bwp
	( 
	.clock(rdclk),
	.clrn((~ aclr)),
	.d(wire_rs_dgwp_gray2bin_bin),
	.q(wire_rs_bwp_q));
	myfifo_alt_synch_pipe   rs_dgwp
	( 
	.clock(rdclk),
	.clrn((~ aclr)),
	.d(delayed_wrptr_g),
	.q(wire_rs_dgwp_q));
	myfifo_alt_synch_pipe1   ws_dgrp
	( 
	.clock(wrclk),
	.clrn((~ aclr)),
	.d(rdptr_g),
	.q(wire_ws_dgrp_q));
	assign
		wire_rdusedw_sub_result = wire_rdusedw_sub_dataa - wire_rdusedw_sub_datab;
	assign
		wire_rdusedw_sub_dataa = wire_rs_bwp_q,
		wire_rdusedw_sub_datab = wire_rs_brp_q;
	myfifo_cmpr   rdempty_eq_comp
	( 
	.aeb(wire_rdempty_eq_comp_aeb),
	.dataa(wire_rs_dgwp_q),
	.datab(rdptr_g));
	myfifo_cmpr   wrfull_eq_comp
	( 
	.aeb(wire_wrfull_eq_comp_aeb),
	.dataa(wire_ws_dgrp_q),
	.datab(wrptr_gs));
	assign
		int_rdempty = wire_rdempty_eq_comp_aeb,
		int_wrfull = wire_wrfull_eq_comp_aeb,
		q = wire_fifo_ram_q_b,
		ram_address_a = {(wire_wrptr_gp_q[4] ^ wire_wrptr_gp_q[3]), wire_wrptr_gp_q[2:0]},
		ram_address_b = {(wire_rdptr_g1p_q[4] ^ wire_rdptr_g1p_q[3]), wire_rdptr_g1p_q[2:0]},
		rdcnt_addr_ena = (valid_rdreq | (~ p0addr)),
		rdempty = int_rdempty,
		rdusedw = {wire_rdusedw_sub_result[3:0]},
		valid_rdreq = (rdreq & (~ int_rdempty)),
		valid_wrreq = (wrreq & (~ int_wrfull)),
		wrfull = int_wrfull,
		wrptr_gs = {(~ wire_wrptr_gp_q[4]), (~ wire_wrptr_gp_q[3]), wire_wrptr_gp_q[2:0]};
endmodule //myfifo_dcfifo
//VALID FILE


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module myfifo (
	aclr,
	data,
	rdclk,
	rdreq,
	wrclk,
	wrreq,
	q,
	rdempty,
	rdusedw,
	wrfull)/* synthesis synthesis_clearbox = 1 */;

	input	  aclr;
	input	[7:0]  data;
	input	  rdclk;
	input	  rdreq;
	input	  wrclk;
	input	  wrreq;
	output	[7:0]  q;
	output	  rdempty;
	output	[3:0]  rdusedw;
	output	  wrfull;

	wire  sub_wire0;
	wire  sub_wire1;
	wire [7:0] sub_wire2;
	wire [3:0] sub_wire3;
	wire  rdempty = sub_wire0;
	wire  wrfull = sub_wire1;
	wire [7:0] q = sub_wire2[7:0];
	wire [3:0] rdusedw = sub_wire3[3:0];

	myfifo_dcfifo	myfifo_dcfifo_component (
				.wrclk (wrclk),
				.rdreq (rdreq),
				.aclr (aclr),
				.rdclk (rdclk),
				.wrreq (wrreq),
				.data (data),
				.rdempty (sub_wire0),
				.wrfull (sub_wire1),
				.q (sub_wire2),
				.rdusedw (sub_wire3));

endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "8"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "8"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: rdusedw 0 0 4 0 OUTPUT NODEFVAL rdusedw[3..0]
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: rdusedw 0 0 4 0 @rdusedw 0 0 4 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL myfifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL myfifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL myfifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL myfifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL myfifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL myfifo_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL myfifo_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL myfifo_wave*.jpg FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL myfifo_syn.v TRUE
// Retrieval info: LIB_FILE: altera_mf