📄 myfifo_syn.v
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ram_block5a_3.logical_ram_name = "ALTSYNCRAM",
ram_block5a_3.mixed_port_feed_through_mode = "dont_care",
ram_block5a_3.operation_mode = "dual_port",
ram_block5a_3.port_a_address_width = 4,
ram_block5a_3.port_a_data_width = 1,
ram_block5a_3.port_a_disable_ce_on_input_registers = "off",
ram_block5a_3.port_a_first_address = 0,
ram_block5a_3.port_a_first_bit_number = 3,
ram_block5a_3.port_a_last_address = 15,
ram_block5a_3.port_a_logical_ram_depth = 16,
ram_block5a_3.port_a_logical_ram_width = 8,
ram_block5a_3.port_b_address_clock = "clock1",
ram_block5a_3.port_b_address_width = 4,
ram_block5a_3.port_b_data_out_clear = "clear1",
ram_block5a_3.port_b_data_out_clock = "clock1",
ram_block5a_3.port_b_data_width = 1,
ram_block5a_3.port_b_disable_ce_on_input_registers = "on",
ram_block5a_3.port_b_disable_ce_on_output_registers = "off",
ram_block5a_3.port_b_first_address = 0,
ram_block5a_3.port_b_first_bit_number = 3,
ram_block5a_3.port_b_last_address = 15,
ram_block5a_3.port_b_logical_ram_depth = 16,
ram_block5a_3.port_b_logical_ram_width = 8,
ram_block5a_3.port_b_read_enable_write_enable_clock = "clock1",
ram_block5a_3.ram_block_type = "AUTO",
ram_block5a_3.lpm_type = "cycloneii_ram_block";
cycloneii_ram_block ram_block5a_4
(
.clk0(clock0),
.clk1(clock1),
.clr1(aclr1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[3:0]}),
.portadatain({data_a[4]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[3:0]}),
.portbaddrstall(addressstall_b),
.portbdataout(wire_ram_block5a_4portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block5a_4.connectivity_checking = "OFF",
ram_block5a_4.logical_ram_name = "ALTSYNCRAM",
ram_block5a_4.mixed_port_feed_through_mode = "dont_care",
ram_block5a_4.operation_mode = "dual_port",
ram_block5a_4.port_a_address_width = 4,
ram_block5a_4.port_a_data_width = 1,
ram_block5a_4.port_a_disable_ce_on_input_registers = "off",
ram_block5a_4.port_a_first_address = 0,
ram_block5a_4.port_a_first_bit_number = 4,
ram_block5a_4.port_a_last_address = 15,
ram_block5a_4.port_a_logical_ram_depth = 16,
ram_block5a_4.port_a_logical_ram_width = 8,
ram_block5a_4.port_b_address_clock = "clock1",
ram_block5a_4.port_b_address_width = 4,
ram_block5a_4.port_b_data_out_clear = "clear1",
ram_block5a_4.port_b_data_out_clock = "clock1",
ram_block5a_4.port_b_data_width = 1,
ram_block5a_4.port_b_disable_ce_on_input_registers = "on",
ram_block5a_4.port_b_disable_ce_on_output_registers = "off",
ram_block5a_4.port_b_first_address = 0,
ram_block5a_4.port_b_first_bit_number = 4,
ram_block5a_4.port_b_last_address = 15,
ram_block5a_4.port_b_logical_ram_depth = 16,
ram_block5a_4.port_b_logical_ram_width = 8,
ram_block5a_4.port_b_read_enable_write_enable_clock = "clock1",
ram_block5a_4.ram_block_type = "AUTO",
ram_block5a_4.lpm_type = "cycloneii_ram_block";
cycloneii_ram_block ram_block5a_5
(
.clk0(clock0),
.clk1(clock1),
.clr1(aclr1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[3:0]}),
.portadatain({data_a[5]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[3:0]}),
.portbaddrstall(addressstall_b),
.portbdataout(wire_ram_block5a_5portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block5a_5.connectivity_checking = "OFF",
ram_block5a_5.logical_ram_name = "ALTSYNCRAM",
ram_block5a_5.mixed_port_feed_through_mode = "dont_care",
ram_block5a_5.operation_mode = "dual_port",
ram_block5a_5.port_a_address_width = 4,
ram_block5a_5.port_a_data_width = 1,
ram_block5a_5.port_a_disable_ce_on_input_registers = "off",
ram_block5a_5.port_a_first_address = 0,
ram_block5a_5.port_a_first_bit_number = 5,
ram_block5a_5.port_a_last_address = 15,
ram_block5a_5.port_a_logical_ram_depth = 16,
ram_block5a_5.port_a_logical_ram_width = 8,
ram_block5a_5.port_b_address_clock = "clock1",
ram_block5a_5.port_b_address_width = 4,
ram_block5a_5.port_b_data_out_clear = "clear1",
ram_block5a_5.port_b_data_out_clock = "clock1",
ram_block5a_5.port_b_data_width = 1,
ram_block5a_5.port_b_disable_ce_on_input_registers = "on",
ram_block5a_5.port_b_disable_ce_on_output_registers = "off",
ram_block5a_5.port_b_first_address = 0,
ram_block5a_5.port_b_first_bit_number = 5,
ram_block5a_5.port_b_last_address = 15,
ram_block5a_5.port_b_logical_ram_depth = 16,
ram_block5a_5.port_b_logical_ram_width = 8,
ram_block5a_5.port_b_read_enable_write_enable_clock = "clock1",
ram_block5a_5.ram_block_type = "AUTO",
ram_block5a_5.lpm_type = "cycloneii_ram_block";
cycloneii_ram_block ram_block5a_6
(
.clk0(clock0),
.clk1(clock1),
.clr1(aclr1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[3:0]}),
.portadatain({data_a[6]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[3:0]}),
.portbaddrstall(addressstall_b),
.portbdataout(wire_ram_block5a_6portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block5a_6.connectivity_checking = "OFF",
ram_block5a_6.logical_ram_name = "ALTSYNCRAM",
ram_block5a_6.mixed_port_feed_through_mode = "dont_care",
ram_block5a_6.operation_mode = "dual_port",
ram_block5a_6.port_a_address_width = 4,
ram_block5a_6.port_a_data_width = 1,
ram_block5a_6.port_a_disable_ce_on_input_registers = "off",
ram_block5a_6.port_a_first_address = 0,
ram_block5a_6.port_a_first_bit_number = 6,
ram_block5a_6.port_a_last_address = 15,
ram_block5a_6.port_a_logical_ram_depth = 16,
ram_block5a_6.port_a_logical_ram_width = 8,
ram_block5a_6.port_b_address_clock = "clock1",
ram_block5a_6.port_b_address_width = 4,
ram_block5a_6.port_b_data_out_clear = "clear1",
ram_block5a_6.port_b_data_out_clock = "clock1",
ram_block5a_6.port_b_data_width = 1,
ram_block5a_6.port_b_disable_ce_on_input_registers = "on",
ram_block5a_6.port_b_disable_ce_on_output_registers = "off",
ram_block5a_6.port_b_first_address = 0,
ram_block5a_6.port_b_first_bit_number = 6,
ram_block5a_6.port_b_last_address = 15,
ram_block5a_6.port_b_logical_ram_depth = 16,
ram_block5a_6.port_b_logical_ram_width = 8,
ram_block5a_6.port_b_read_enable_write_enable_clock = "clock1",
ram_block5a_6.ram_block_type = "AUTO",
ram_block5a_6.lpm_type = "cycloneii_ram_block";
cycloneii_ram_block ram_block5a_7
(
.clk0(clock0),
.clk1(clock1),
.clr1(aclr1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[3:0]}),
.portadatain({data_a[7]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[3:0]}),
.portbaddrstall(addressstall_b),
.portbdataout(wire_ram_block5a_7portbdataout[0:0]),
.portbrewe(1'b1)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clr0(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block5a_7.connectivity_checking = "OFF",
ram_block5a_7.logical_ram_name = "ALTSYNCRAM",
ram_block5a_7.mixed_port_feed_through_mode = "dont_care",
ram_block5a_7.operation_mode = "dual_port",
ram_block5a_7.port_a_address_width = 4,
ram_block5a_7.port_a_data_width = 1,
ram_block5a_7.port_a_disable_ce_on_input_registers = "off",
ram_block5a_7.port_a_first_address = 0,
ram_block5a_7.port_a_first_bit_number = 7,
ram_block5a_7.port_a_last_address = 15,
ram_block5a_7.port_a_logical_ram_depth = 16,
ram_block5a_7.port_a_logical_ram_width = 8,
ram_block5a_7.port_b_address_clock = "clock1",
ram_block5a_7.port_b_address_width = 4,
ram_block5a_7.port_b_data_out_clear = "clear1",
ram_block5a_7.port_b_data_out_clock = "clock1",
ram_block5a_7.port_b_data_width = 1,
ram_block5a_7.port_b_disable_ce_on_input_registers = "on",
ram_block5a_7.port_b_disable_ce_on_output_registers = "off",
ram_block5a_7.port_b_first_address = 0,
ram_block5a_7.port_b_first_bit_number = 7,
ram_block5a_7.port_b_last_address = 15,
ram_block5a_7.port_b_logical_ram_depth = 16,
ram_block5a_7.port_b_logical_ram_width = 8,
ram_block5a_7.port_b_read_enable_write_enable_clock = "clock1",
ram_block5a_7.ram_block_type = "AUTO",
ram_block5a_7.lpm_type = "cycloneii_ram_block";
assign
address_a_wire = address_a,
address_b_wire = address_b,
q_b = {wire_ram_block5a_7portbdataout[0], wire_ram_block5a_6portbdataout[0], wire_ram_block5a_5portbdataout[0], wire_ram_block5a_4portbdataout[0], wire_ram_block5a_3portbdataout[0], wire_ram_block5a_2portbdataout[0], wire_ram_block5a_1portbdataout[0], wire_ram_block5a_0portbdataout[0]};
endmodule //myfifo_altsyncram
//dffpipe DELAY=1 WIDTH=1 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF;PRESERVE_REGISTER=ON;suppress_da_rule_internal=c106;suppress_da_rule_internal=r105
//VERSION_BEGIN 8.1 cbx_mgl 2008:08:08:15:16:18:SJ cbx_stratixii 2008:08:07:13:54:47:SJ cbx_util_mgl 2008:07:18:09:58:54:SJ VERSION_END
//synthesis_resources = reg 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF;PRESERVE_REGISTER=ON;suppress_da_rule_internal=c106;suppress_da_rule_internal=r105"} *)
module myfifo_dffpipe
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [0:0] d;
output [0:0] q;
reg [0:0] dffe6a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe6a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe6a <= {1{1'b1}};
else if (clrn == 1'b0) dffe6a <= 1'b0;
else if (ena == 1'b1) dffe6a <= (d & (~ sclr));
assign
ena = 1'b1,
prn = 1'b1,
q = dffe6a,
sclr = 1'b0;
endmodule //myfifo_dffpipe
//dffpipe DELAY=1 WIDTH=5 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF;suppress_da_rule_internal=r105
//VERSION_BEGIN 8.1 cbx_mgl 2008:08:08:15:16:18:SJ cbx_stratixii 2008:08:07:13:54:47:SJ cbx_util_mgl 2008:07:18:09:58:54:SJ VERSION_END
//synthesis_resources = reg 5
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF;suppress_da_rule_internal=r105"} *)
module myfifo_dffpipe1
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [4:0] d;
output [4:0] q;
reg [4:0] dffe7a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe7a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe7a <= {5{1'b1}};
else if (clrn == 1'b0) dffe7a <= 5'b0;
else if (ena == 1'b1) dffe7a <= (d & {5{(~ sclr)}});
assign
ena = 1'b1,
prn = 1'b1,
q = dffe7a,
sclr = 1'b0;
endmodule //myfifo_dffpipe1
//dffpipe DELAY=2 WIDTH=5 clock clrn d q ALTERA_INTERNAL_OPTIONS=X_ON_VIOLATION_OPTION=OFF;suppress_da_rule_internal=r105
//VERSION_BEGIN 8.1 cbx_a_gray2bin 2008:05:19:09:32:04:SJ cbx_a_graycounter 2008:05:19:09:39:53:SJ cbx_altdpram 2008:05:19:10:27:12:SJ cbx_altsyncram 2008:08:26:11:57:11:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_dcfifo 2008:09:07:22:36:06:SJ cbx_fifo_common 2008:05:19:10:54:06:SJ cbx_flex10ke 2008:05:19:10:53:03:SJ cbx_lpm_add_sub 2008:05:19:10:49:01:SJ cbx_lpm_compare 2008:09:01:07:44:05:SJ cbx_lpm_counter 2008:05:19:10:42:20:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_lpm_mux 2008:05:19:10:30:36:SJ cbx_mgl 2008:08:08:15:16:18:SJ cbx_scfifo 2008:05:19:10:25:30:SJ cbx_stratix 2008:08:05:17:10:23:SJ cbx_stratixii 2008:08:07:13:54:47:SJ cbx_stratixiii 2008:07:11:13:32:02:SJ cbx_util_mgl 2008:07:18:09:58:54:SJ VERSION_END
//dffpipe DELAY=2 WIDTH=5 clock clrn d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
//VERSION_BEGIN 8.1 cbx_mgl 2008:08:08:15:16:18:SJ cbx_stratixii 2008:08:07:13:54:47:SJ cbx_util_mgl 2008:07:18:09:58:54:SJ VERSION_END
//synthesis_resources = reg 10
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF"} *)
module myfifo_dffpipe2
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [4:0] d;
output [4:0] q;
reg [4:0] dffe10a;
reg [4:0] dffe9a;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe10a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe10a <= {5{1'b1}};
else if (clrn == 1'b0) dffe10a <= 5'b0;
else if (ena == 1'b1) dffe10a <= (dffe9a & {5{(~ sclr)}});
// synopsys translate_off
initial
dffe9a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe9a <= {5{1'b1}};
else if (clrn == 1'b0) dffe9a <= 5'b0;
else if (ena == 1'b1) dffe9a <= (d & {5{(~ sclr)}});
assign
ena = 1'b1,
prn = 1'b1,
q = dffe10a,
sclr = 1'b0;
endmodule //myfifo_dffpipe2
//synthesis_resources = reg 10
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"X_ON_VIOLATION_OPTION=OFF;suppress_da_rule_internal=r105"} *)
module myfifo_alt_synch_pipe
(
clock,
clrn,
d,
q) /* synthesis synthesis_clearbox=1 */;
input clock;
input clrn;
input [4:0] d;
output [4:0] q;
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