myfifo_syn.v

fifo(1-6:1):using ip-code and rd wd interface

	clock,
	cnt_en,
	q) /* synthesis synthesis_clearbox=1 */;
	input   aclr;
	input   clock;
	input   cnt_en;
	output   [4:0]  q;

	wire  [4:0]   wire_countera_combout;
	wire  [0:0]   wire_countera_0cout;
	wire  [0:0]   wire_countera_1cout;
	wire  [0:0]   wire_countera_2cout;
	wire  [0:0]   wire_countera_3cout;
	wire  wire_parity_combout;
	wire  wire_parity_cout;
	reg	[4:0]	counter_ffa;
	reg	parity_ff;
	wire sclr;
	wire updown;

	cycloneii_lcell_comb   countera_0
	( 
	.cin(wire_parity_cout),
	.combout(wire_countera_combout[0:0]),
	.cout(wire_countera_0cout[0:0]),
	.dataa(cnt_en),
	.datab(counter_ffa[0:0]),
	.datad(1'b1),
	.datac(1'b0)
	);
	defparam
		countera_0.lut_mask = 16'hC6A0,
		countera_0.sum_lutc_input = "cin",
		countera_0.lpm_type = "cycloneii_lcell_comb";
	cycloneii_lcell_comb   countera_1
	( 
	.cin(wire_countera_0cout[0:0]),
	.combout(wire_countera_combout[1:1]),
	.cout(wire_countera_1cout[0:0]),
	.dataa(counter_ffa[0:0]),
	.datab(counter_ffa[1:1]),
	.datad(1'b1),
	.datac(1'b0)
	);
	defparam
		countera_1.lut_mask = 16'h6C50,
		countera_1.sum_lutc_input = "cin",
		countera_1.lpm_type = "cycloneii_lcell_comb";
	cycloneii_lcell_comb   countera_2
	( 
	.cin(wire_countera_1cout[0:0]),
	.combout(wire_countera_combout[2:2]),
	.cout(wire_countera_2cout[0:0]),
	.dataa(counter_ffa[1:1]),
	.datab(counter_ffa[2:2]),
	.datad(1'b1),
	.datac(1'b0)
	);
	defparam
		countera_2.lut_mask = 16'h6C50,
		countera_2.sum_lutc_input = "cin",
		countera_2.lpm_type = "cycloneii_lcell_comb";
	cycloneii_lcell_comb   countera_3
	( 
	.cin(wire_countera_2cout[0:0]),
	.combout(wire_countera_combout[3:3]),
	.cout(wire_countera_3cout[0:0]),
	.dataa(counter_ffa[2:2]),
	.datab(counter_ffa[3:3]),
	.datad(1'b1),
	.datac(1'b0)
	);
	defparam
		countera_3.lut_mask = 16'h6C50,
		countera_3.sum_lutc_input = "cin",
		countera_3.lpm_type = "cycloneii_lcell_comb";
	cycloneii_lcell_comb   countera_4
	( 
	.cin(wire_countera_3cout[0:0]),
	.combout(wire_countera_combout[4:4]),
	.cout(),
	.dataa(counter_ffa[4:4]),
	.datad(1'b1),
	.datab(1'b0),
	.datac(1'b0)
	);
	defparam
		countera_4.lut_mask = 16'h5A5A,
		countera_4.sum_lutc_input = "cin",
		countera_4.lpm_type = "cycloneii_lcell_comb";
	cycloneii_lcell_comb   parity
	( 
	.cin((~ updown)),
	.combout(wire_parity_combout),
	.cout(wire_parity_cout),
	.dataa(cnt_en),
	.datab(parity_ff),
	.datad(1'b1),
	.datac(1'b0)
	);
	defparam
		parity.lut_mask = 16'h6628,
		parity.sum_lutc_input = "cin",
		parity.lpm_type = "cycloneii_lcell_comb";
	// synopsys translate_off
	initial
		counter_ffa[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) counter_ffa[0:0] <= 1'b0;
		else
			if (sclr == 1'b1) counter_ffa[0:0] <= 1'b0;
			else  counter_ffa[0:0] <= wire_countera_combout[0:0];
	// synopsys translate_off
	initial
		counter_ffa[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) counter_ffa[1:1] <= 1'b0;
		else
			if (sclr == 1'b1) counter_ffa[1:1] <= 1'b0;
			else  counter_ffa[1:1] <= wire_countera_combout[1:1];
	// synopsys translate_off
	initial
		counter_ffa[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) counter_ffa[2:2] <= 1'b0;
		else
			if (sclr == 1'b1) counter_ffa[2:2] <= 1'b0;
			else  counter_ffa[2:2] <= wire_countera_combout[2:2];
	// synopsys translate_off
	initial
		counter_ffa[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) counter_ffa[3:3] <= 1'b0;
		else
			if (sclr == 1'b1) counter_ffa[3:3] <= 1'b0;
			else  counter_ffa[3:3] <= wire_countera_combout[3:3];
	// synopsys translate_off
	initial
		counter_ffa[4:4] = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) counter_ffa[4:4] <= 1'b0;
		else
			if (sclr == 1'b1) counter_ffa[4:4] <= 1'b0;
			else  counter_ffa[4:4] <= wire_countera_combout[4:4];
	// synopsys translate_off
	initial
		parity_ff = 0;
	// synopsys translate_on
	always @ ( posedge clock or  posedge aclr)
		if (aclr == 1'b1) parity_ff <= 1'b0;
		else
			if (sclr == 1'b1) parity_ff <= 1'b0;
			else  parity_ff <= wire_parity_combout;
	assign
		q = counter_ffa,
		sclr = 1'b0,
		updown = 1'b1;
endmodule //myfifo_a_graycounter2


//altsyncram ADDRESS_REG_B="CLOCK1" CLOCK_ENABLE_INPUT_B="BYPASS" DEVICE_FAMILY="Cyclone II" OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="CLEAR1" OUTDATA_REG_B="CLOCK1" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=4 WIDTHAD_B=4 aclr1 address_a address_b addressstall_b clock0 clock1 clocken1 data_a q_b wren_a ALTERA_INTERNAL_OPTIONS=suppress_da_rule_internal=r105
//VERSION_BEGIN 8.1 cbx_altsyncram 2008:08:26:11:57:11:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2008:05:19:10:49:01:SJ cbx_lpm_compare 2008:09:01:07:44:05:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_lpm_mux 2008:05:19:10:30:36:SJ cbx_mgl 2008:08:08:15:16:18:SJ cbx_stratix 2008:08:05:17:10:23:SJ cbx_stratixii 2008:08:07:13:54:47:SJ cbx_stratixiii 2008:07:11:13:32:02:SJ cbx_util_mgl 2008:07:18:09:58:54:SJ  VERSION_END

//synthesis_resources = M4K 1 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"suppress_da_rule_internal=r105;OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"} *)
module  myfifo_altsyncram
	( 
	aclr1,
	address_a,
	address_b,
	addressstall_b,
	clock0,
	clock1,
	clocken1,
	data_a,
	q_b,
	wren_a) /* synthesis synthesis_clearbox=1 */;
	input   aclr1;
	input   [3:0]  address_a;
	input   [3:0]  address_b;
	input   addressstall_b;
	input   clock0;
	input   clock1;
	input   clocken1;
	input   [7:0]  data_a;
	output   [7:0]  q_b;
	input   wren_a;

	wire  [0:0]   wire_ram_block5a_0portbdataout;
	wire  [0:0]   wire_ram_block5a_1portbdataout;
	wire  [0:0]   wire_ram_block5a_2portbdataout;
	wire  [0:0]   wire_ram_block5a_3portbdataout;
	wire  [0:0]   wire_ram_block5a_4portbdataout;
	wire  [0:0]   wire_ram_block5a_5portbdataout;
	wire  [0:0]   wire_ram_block5a_6portbdataout;
	wire  [0:0]   wire_ram_block5a_7portbdataout;
	wire  [3:0]  address_a_wire;
	wire  [3:0]  address_b_wire;

	cycloneii_ram_block   ram_block5a_0
	( 
	.clk0(clock0),
	.clk1(clock1),
	.clr1(aclr1),
	.ena0(wren_a),
	.ena1(clocken1),
	.portaaddr({address_a_wire[3:0]}),
	.portadatain({data_a[0]}),
	.portadataout(),
	.portawe(wren_a),
	.portbaddr({address_b_wire[3:0]}),
	.portbaddrstall(addressstall_b),
	.portbdataout(wire_ram_block5a_0portbdataout[0:0]),
	.portbrewe(1'b1)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clr0(1'b0),
	.portaaddrstall(1'b0),
	.portabyteenamasks({1{1'b1}}),
	.portbbyteenamasks({1{1'b1}}),
	.portbdatain({1{1'b0}})
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(1'b1),
	.devpor(1'b1)
	// synopsys translate_on
	);
	defparam
		ram_block5a_0.connectivity_checking = "OFF",
		ram_block5a_0.logical_ram_name = "ALTSYNCRAM",
		ram_block5a_0.mixed_port_feed_through_mode = "dont_care",
		ram_block5a_0.operation_mode = "dual_port",
		ram_block5a_0.port_a_address_width = 4,
		ram_block5a_0.port_a_data_width = 1,
		ram_block5a_0.port_a_disable_ce_on_input_registers = "off",
		ram_block5a_0.port_a_first_address = 0,
		ram_block5a_0.port_a_first_bit_number = 0,
		ram_block5a_0.port_a_last_address = 15,
		ram_block5a_0.port_a_logical_ram_depth = 16,
		ram_block5a_0.port_a_logical_ram_width = 8,
		ram_block5a_0.port_b_address_clock = "clock1",
		ram_block5a_0.port_b_address_width = 4,
		ram_block5a_0.port_b_data_out_clear = "clear1",
		ram_block5a_0.port_b_data_out_clock = "clock1",
		ram_block5a_0.port_b_data_width = 1,
		ram_block5a_0.port_b_disable_ce_on_input_registers = "on",
		ram_block5a_0.port_b_disable_ce_on_output_registers = "off",
		ram_block5a_0.port_b_first_address = 0,
		ram_block5a_0.port_b_first_bit_number = 0,
		ram_block5a_0.port_b_last_address = 15,
		ram_block5a_0.port_b_logical_ram_depth = 16,
		ram_block5a_0.port_b_logical_ram_width = 8,
		ram_block5a_0.port_b_read_enable_write_enable_clock = "clock1",
		ram_block5a_0.ram_block_type = "AUTO",
		ram_block5a_0.lpm_type = "cycloneii_ram_block";
	cycloneii_ram_block   ram_block5a_1
	( 
	.clk0(clock0),
	.clk1(clock1),
	.clr1(aclr1),
	.ena0(wren_a),
	.ena1(clocken1),
	.portaaddr({address_a_wire[3:0]}),
	.portadatain({data_a[1]}),
	.portadataout(),
	.portawe(wren_a),
	.portbaddr({address_b_wire[3:0]}),
	.portbaddrstall(addressstall_b),
	.portbdataout(wire_ram_block5a_1portbdataout[0:0]),
	.portbrewe(1'b1)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clr0(1'b0),
	.portaaddrstall(1'b0),
	.portabyteenamasks({1{1'b1}}),
	.portbbyteenamasks({1{1'b1}}),
	.portbdatain({1{1'b0}})
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(1'b1),
	.devpor(1'b1)
	// synopsys translate_on
	);
	defparam
		ram_block5a_1.connectivity_checking = "OFF",
		ram_block5a_1.logical_ram_name = "ALTSYNCRAM",
		ram_block5a_1.mixed_port_feed_through_mode = "dont_care",
		ram_block5a_1.operation_mode = "dual_port",
		ram_block5a_1.port_a_address_width = 4,
		ram_block5a_1.port_a_data_width = 1,
		ram_block5a_1.port_a_disable_ce_on_input_registers = "off",
		ram_block5a_1.port_a_first_address = 0,
		ram_block5a_1.port_a_first_bit_number = 1,
		ram_block5a_1.port_a_last_address = 15,
		ram_block5a_1.port_a_logical_ram_depth = 16,
		ram_block5a_1.port_a_logical_ram_width = 8,
		ram_block5a_1.port_b_address_clock = "clock1",
		ram_block5a_1.port_b_address_width = 4,
		ram_block5a_1.port_b_data_out_clear = "clear1",
		ram_block5a_1.port_b_data_out_clock = "clock1",
		ram_block5a_1.port_b_data_width = 1,
		ram_block5a_1.port_b_disable_ce_on_input_registers = "on",
		ram_block5a_1.port_b_disable_ce_on_output_registers = "off",
		ram_block5a_1.port_b_first_address = 0,
		ram_block5a_1.port_b_first_bit_number = 1,
		ram_block5a_1.port_b_last_address = 15,
		ram_block5a_1.port_b_logical_ram_depth = 16,
		ram_block5a_1.port_b_logical_ram_width = 8,
		ram_block5a_1.port_b_read_enable_write_enable_clock = "clock1",
		ram_block5a_1.ram_block_type = "AUTO",
		ram_block5a_1.lpm_type = "cycloneii_ram_block";
	cycloneii_ram_block   ram_block5a_2
	( 
	.clk0(clock0),
	.clk1(clock1),
	.clr1(aclr1),
	.ena0(wren_a),
	.ena1(clocken1),
	.portaaddr({address_a_wire[3:0]}),
	.portadatain({data_a[2]}),
	.portadataout(),
	.portawe(wren_a),
	.portbaddr({address_b_wire[3:0]}),
	.portbaddrstall(addressstall_b),
	.portbdataout(wire_ram_block5a_2portbdataout[0:0]),
	.portbrewe(1'b1)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clr0(1'b0),
	.portaaddrstall(1'b0),
	.portabyteenamasks({1{1'b1}}),
	.portbbyteenamasks({1{1'b1}}),
	.portbdatain({1{1'b0}})
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(1'b1),
	.devpor(1'b1)
	// synopsys translate_on
	);
	defparam
		ram_block5a_2.connectivity_checking = "OFF",
		ram_block5a_2.logical_ram_name = "ALTSYNCRAM",
		ram_block5a_2.mixed_port_feed_through_mode = "dont_care",
		ram_block5a_2.operation_mode = "dual_port",
		ram_block5a_2.port_a_address_width = 4,
		ram_block5a_2.port_a_data_width = 1,
		ram_block5a_2.port_a_disable_ce_on_input_registers = "off",
		ram_block5a_2.port_a_first_address = 0,
		ram_block5a_2.port_a_first_bit_number = 2,
		ram_block5a_2.port_a_last_address = 15,
		ram_block5a_2.port_a_logical_ram_depth = 16,
		ram_block5a_2.port_a_logical_ram_width = 8,
		ram_block5a_2.port_b_address_clock = "clock1",
		ram_block5a_2.port_b_address_width = 4,
		ram_block5a_2.port_b_data_out_clear = "clear1",
		ram_block5a_2.port_b_data_out_clock = "clock1",
		ram_block5a_2.port_b_data_width = 1,
		ram_block5a_2.port_b_disable_ce_on_input_registers = "on",
		ram_block5a_2.port_b_disable_ce_on_output_registers = "off",
		ram_block5a_2.port_b_first_address = 0,
		ram_block5a_2.port_b_first_bit_number = 2,
		ram_block5a_2.port_b_last_address = 15,
		ram_block5a_2.port_b_logical_ram_depth = 16,
		ram_block5a_2.port_b_logical_ram_width = 8,
		ram_block5a_2.port_b_read_enable_write_enable_clock = "clock1",
		ram_block5a_2.ram_block_type = "AUTO",
		ram_block5a_2.lpm_type = "cycloneii_ram_block";
	cycloneii_ram_block   ram_block5a_3
	( 
	.clk0(clock0),
	.clk1(clock1),
	.clr1(aclr1),
	.ena0(wren_a),
	.ena1(clocken1),
	.portaaddr({address_a_wire[3:0]}),
	.portadatain({data_a[3]}),
	.portadataout(),
	.portawe(wren_a),
	.portbaddr({address_b_wire[3:0]}),
	.portbaddrstall(addressstall_b),
	.portbdataout(wire_ram_block5a_3portbdataout[0:0]),
	.portbrewe(1'b1)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.clr0(1'b0),
	.portaaddrstall(1'b0),
	.portabyteenamasks({1{1'b1}}),
	.portbbyteenamasks({1{1'b1}}),
	.portbdatain({1{1'b0}})
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(1'b1),
	.devpor(1'b1)
	// synopsys translate_on
	);
	defparam
		ram_block5a_3.connectivity_checking = "OFF",