📄 myfifo_syn.v
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// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: myfifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 8.1 Build 163 10/28/2008 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2008 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//dcfifo_mixed_widths DEVICE_FAMILY="Cyclone II" LPM_NUMWORDS=16 LPM_SHOWAHEAD="OFF" LPM_WIDTH=8 LPM_WIDTH_R=8 LPM_WIDTHU=4 LPM_WIDTHU_R=4 OVERFLOW_CHECKING="ON" RDSYNC_DELAYPIPE=4 UNDERFLOW_CHECKING="ON" USE_EAB="ON" WRITE_ACLR_SYNCH="OFF" WRSYNC_DELAYPIPE=4 aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq INTENDED_DEVICE_FAMILY="Cyclone II" ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
//VERSION_BEGIN 8.1 cbx_a_gray2bin 2008:05:19:09:32:04:SJ cbx_a_graycounter 2008:05:19:09:39:53:SJ cbx_altdpram 2008:05:19:10:27:12:SJ cbx_altsyncram 2008:08:26:11:57:11:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_dcfifo 2008:09:07:22:36:06:SJ cbx_fifo_common 2008:05:19:10:54:06:SJ cbx_flex10ke 2008:05:19:10:53:03:SJ cbx_lpm_add_sub 2008:05:19:10:49:01:SJ cbx_lpm_compare 2008:09:01:07:44:05:SJ cbx_lpm_counter 2008:05:19:10:42:20:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_lpm_mux 2008:05:19:10:30:36:SJ cbx_mgl 2008:08:08:15:16:18:SJ cbx_scfifo 2008:05:19:10:25:30:SJ cbx_stratix 2008:08:05:17:10:23:SJ cbx_stratixii 2008:08:07:13:54:47:SJ cbx_stratixiii 2008:07:11:13:32:02:SJ cbx_util_mgl 2008:07:18:09:58:54:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//a_gray2bin device_family="Cyclone II" WIDTH=5 bin gray
//VERSION_BEGIN 8.1 cbx_a_gray2bin 2008:05:19:09:32:04:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module myfifo_a_gray2bin
(
bin,
gray) /* synthesis synthesis_clearbox=1 */;
output [4:0] bin;
input [4:0] gray;
wire xor0;
wire xor1;
wire xor2;
wire xor3;
assign
bin = {gray[4], xor3, xor2, xor1, xor0},
xor0 = (gray[0] ^ xor1),
xor1 = (gray[1] ^ xor2),
xor2 = (gray[2] ^ xor3),
xor3 = (gray[4] ^ gray[3]);
endmodule //myfifo_a_gray2bin
//a_graycounter DEVICE_FAMILY="Cyclone II" WIDTH=5 aclr clock cnt_en q
//VERSION_BEGIN 8.1 cbx_a_gray2bin 2008:05:19:09:32:04:SJ cbx_a_graycounter 2008:05:19:09:39:53:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_flex10ke 2008:05:19:10:53:03:SJ cbx_mgl 2008:08:08:15:16:18:SJ cbx_stratix 2008:08:05:17:10:23:SJ cbx_stratixii 2008:08:07:13:54:47:SJ VERSION_END
//synthesis_resources = lut 6 reg 6
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module myfifo_a_graycounter
(
aclr,
clock,
cnt_en,
q) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clock;
input cnt_en;
output [4:0] q;
wire [4:0] wire_countera_combout;
wire [0:0] wire_countera_0cout;
wire [0:0] wire_countera_1cout;
wire [0:0] wire_countera_2cout;
wire [0:0] wire_countera_3cout;
wire wire_parity_combout;
wire wire_parity_cout;
reg [4:0] counter_ffa;
reg parity_ff;
wire sclr;
wire updown;
cycloneii_lcell_comb countera_0
(
.cin(wire_parity_cout),
.combout(wire_countera_combout[0:0]),
.cout(wire_countera_0cout[0:0]),
.dataa(cnt_en),
.datab(counter_ffa[0:0]),
.datad(1'b1),
.datac(1'b0)
);
defparam
countera_0.lut_mask = 16'hC6A0,
countera_0.sum_lutc_input = "cin",
countera_0.lpm_type = "cycloneii_lcell_comb";
cycloneii_lcell_comb countera_1
(
.cin(wire_countera_0cout[0:0]),
.combout(wire_countera_combout[1:1]),
.cout(wire_countera_1cout[0:0]),
.dataa(counter_ffa[0:0]),
.datab(counter_ffa[1:1]),
.datad(1'b1),
.datac(1'b0)
);
defparam
countera_1.lut_mask = 16'h6C50,
countera_1.sum_lutc_input = "cin",
countera_1.lpm_type = "cycloneii_lcell_comb";
cycloneii_lcell_comb countera_2
(
.cin(wire_countera_1cout[0:0]),
.combout(wire_countera_combout[2:2]),
.cout(wire_countera_2cout[0:0]),
.dataa(counter_ffa[1:1]),
.datab(counter_ffa[2:2]),
.datad(1'b1),
.datac(1'b0)
);
defparam
countera_2.lut_mask = 16'h6C50,
countera_2.sum_lutc_input = "cin",
countera_2.lpm_type = "cycloneii_lcell_comb";
cycloneii_lcell_comb countera_3
(
.cin(wire_countera_2cout[0:0]),
.combout(wire_countera_combout[3:3]),
.cout(wire_countera_3cout[0:0]),
.dataa(counter_ffa[2:2]),
.datab(counter_ffa[3:3]),
.datad(1'b1),
.datac(1'b0)
);
defparam
countera_3.lut_mask = 16'h6C50,
countera_3.sum_lutc_input = "cin",
countera_3.lpm_type = "cycloneii_lcell_comb";
cycloneii_lcell_comb countera_4
(
.cin(wire_countera_3cout[0:0]),
.combout(wire_countera_combout[4:4]),
.cout(),
.dataa(counter_ffa[4:4]),
.datad(1'b1),
.datab(1'b0),
.datac(1'b0)
);
defparam
countera_4.lut_mask = 16'h5A5A,
countera_4.sum_lutc_input = "cin",
countera_4.lpm_type = "cycloneii_lcell_comb";
cycloneii_lcell_comb parity
(
.cin((~ updown)),
.combout(wire_parity_combout),
.cout(wire_parity_cout),
.dataa(cnt_en),
.datab(parity_ff),
.datad(1'b1),
.datac(1'b0)
);
defparam
parity.lut_mask = 16'h6628,
parity.sum_lutc_input = "cin",
parity.lpm_type = "cycloneii_lcell_comb";
// synopsys translate_off
initial
counter_ffa[0:0] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) counter_ffa[0:0] <= 1'b0;
else
if (sclr == 1'b1) counter_ffa[0:0] <= 1'b0;
else counter_ffa[0:0] <= wire_countera_combout[0:0];
// synopsys translate_off
initial
counter_ffa[1:1] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) counter_ffa[1:1] <= 1'b0;
else
if (sclr == 1'b1) counter_ffa[1:1] <= 1'b0;
else counter_ffa[1:1] <= wire_countera_combout[1:1];
// synopsys translate_off
initial
counter_ffa[2:2] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) counter_ffa[2:2] <= 1'b0;
else
if (sclr == 1'b1) counter_ffa[2:2] <= 1'b0;
else counter_ffa[2:2] <= wire_countera_combout[2:2];
// synopsys translate_off
initial
counter_ffa[3:3] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) counter_ffa[3:3] <= 1'b0;
else
if (sclr == 1'b1) counter_ffa[3:3] <= 1'b0;
else counter_ffa[3:3] <= wire_countera_combout[3:3];
// synopsys translate_off
initial
counter_ffa[4:4] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) counter_ffa[4:4] <= 1'b0;
else
if (sclr == 1'b1) counter_ffa[4:4] <= 1'b0;
else counter_ffa[4:4] <= wire_countera_combout[4:4];
// synopsys translate_off
initial
parity_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) parity_ff <= 1'b0;
else
if (sclr == 1'b1) parity_ff <= 1'b0;
else parity_ff <= wire_parity_combout;
assign
q = counter_ffa,
sclr = 1'b0,
updown = 1'b1;
endmodule //myfifo_a_graycounter
//a_graycounter DEVICE_FAMILY="Cyclone II" PVALUE=1 WIDTH=5 aclr clock cnt_en q ALTERA_INTERNAL_OPTIONS=suppress_da_rule_internal=s102
//VERSION_BEGIN 8.1 cbx_a_gray2bin 2008:05:19:09:32:04:SJ cbx_a_graycounter 2008:05:19:09:39:53:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_flex10ke 2008:05:19:10:53:03:SJ cbx_mgl 2008:08:08:15:16:18:SJ cbx_stratix 2008:08:05:17:10:23:SJ cbx_stratixii 2008:08:07:13:54:47:SJ VERSION_END
//synthesis_resources = lut 6 reg 6
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"suppress_da_rule_internal=s102;{-to counter_ffa[0]} POWER_UP_LEVEL=HIGH"} *)
module myfifo_a_graycounter1
(
aclr,
clock,
cnt_en,
q) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clock;
input cnt_en;
output [4:0] q;
wire [4:0] wire_countera_combout;
wire [0:0] wire_countera_0cout;
wire [0:0] wire_countera_1cout;
wire [0:0] wire_countera_2cout;
wire [0:0] wire_countera_3cout;
wire wire_parity_combout;
wire wire_parity_cout;
reg [4:0] counter_ffa;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
reg parity_ff;
wire sclr;
wire updown;
cycloneii_lcell_comb countera_0
(
.cin(wire_parity_cout),
.combout(wire_countera_combout[0:0]),
.cout(wire_countera_0cout[0:0]),
.dataa(cnt_en),
.datab(counter_ffa[0:0]),
.datad(1'b1),
.datac(1'b0)
);
defparam
countera_0.lut_mask = 16'hC6A0,
countera_0.sum_lutc_input = "cin",
countera_0.lpm_type = "cycloneii_lcell_comb";
cycloneii_lcell_comb countera_1
(
.cin(wire_countera_0cout[0:0]),
.combout(wire_countera_combout[1:1]),
.cout(wire_countera_1cout[0:0]),
.dataa(counter_ffa[0:0]),
.datab(counter_ffa[1:1]),
.datad(1'b1),
.datac(1'b0)
);
defparam
countera_1.lut_mask = 16'h6C50,
countera_1.sum_lutc_input = "cin",
countera_1.lpm_type = "cycloneii_lcell_comb";
cycloneii_lcell_comb countera_2
(
.cin(wire_countera_1cout[0:0]),
.combout(wire_countera_combout[2:2]),
.cout(wire_countera_2cout[0:0]),
.dataa(counter_ffa[1:1]),
.datab(counter_ffa[2:2]),
.datad(1'b1),
.datac(1'b0)
);
defparam
countera_2.lut_mask = 16'h6C50,
countera_2.sum_lutc_input = "cin",
countera_2.lpm_type = "cycloneii_lcell_comb";
cycloneii_lcell_comb countera_3
(
.cin(wire_countera_2cout[0:0]),
.combout(wire_countera_combout[3:3]),
.cout(wire_countera_3cout[0:0]),
.dataa(counter_ffa[2:2]),
.datab(counter_ffa[3:3]),
.datad(1'b1),
.datac(1'b0)
);
defparam
countera_3.lut_mask = 16'h6C50,
countera_3.sum_lutc_input = "cin",
countera_3.lpm_type = "cycloneii_lcell_comb";
cycloneii_lcell_comb countera_4
(
.cin(wire_countera_3cout[0:0]),
.combout(wire_countera_combout[4:4]),
.cout(),
.dataa(counter_ffa[4:4]),
.datad(1'b1),
.datab(1'b0),
.datac(1'b0)
);
defparam
countera_4.lut_mask = 16'h5A5A,
countera_4.sum_lutc_input = "cin",
countera_4.lpm_type = "cycloneii_lcell_comb";
cycloneii_lcell_comb parity
(
.cin(updown),
.combout(wire_parity_combout),
.cout(wire_parity_cout),
.dataa(cnt_en),
.datab((~ parity_ff)),
.datad(1'b1),
.datac(1'b0)
);
defparam
parity.lut_mask = 16'h9928,
parity.sum_lutc_input = "cin",
parity.lpm_type = "cycloneii_lcell_comb";
// synopsys translate_off
initial
counter_ffa[0:0] = {1{1'b1}};
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) counter_ffa[0:0] <= {1{1'b1}};
else
if (sclr == 1'b1) counter_ffa[0:0] <= 1'b0;
else counter_ffa[0:0] <= wire_countera_combout[0:0];
// synopsys translate_off
initial
counter_ffa[1:1] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) counter_ffa[1:1] <= 1'b0;
else
if (sclr == 1'b1) counter_ffa[1:1] <= 1'b0;
else counter_ffa[1:1] <= wire_countera_combout[1:1];
// synopsys translate_off
initial
counter_ffa[2:2] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) counter_ffa[2:2] <= 1'b0;
else
if (sclr == 1'b1) counter_ffa[2:2] <= 1'b0;
else counter_ffa[2:2] <= wire_countera_combout[2:2];
// synopsys translate_off
initial
counter_ffa[3:3] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) counter_ffa[3:3] <= 1'b0;
else
if (sclr == 1'b1) counter_ffa[3:3] <= 1'b0;
else counter_ffa[3:3] <= wire_countera_combout[3:3];
// synopsys translate_off
initial
counter_ffa[4:4] = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) counter_ffa[4:4] <= 1'b0;
else
if (sclr == 1'b1) counter_ffa[4:4] <= 1'b0;
else counter_ffa[4:4] <= wire_countera_combout[4:4];
// synopsys translate_off
initial
parity_ff = {1{1'b1}};
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) parity_ff <= {1{1'b1}};
else
if (sclr == 1'b1) parity_ff <= 1'b0;
else parity_ff <= wire_parity_combout;
assign
q = counter_ffa,
sclr = 1'b0,
updown = 1'b1;
endmodule //myfifo_a_graycounter1
//a_graycounter DEVICE_FAMILY="Cyclone II" PVALUE=0 WIDTH=5 aclr clock cnt_en q ALTERA_INTERNAL_OPTIONS=suppress_da_rule_internal=s102
//VERSION_BEGIN 8.1 cbx_a_gray2bin 2008:05:19:09:32:04:SJ cbx_a_graycounter 2008:05:19:09:39:53:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_flex10ke 2008:05:19:10:53:03:SJ cbx_mgl 2008:08:08:15:16:18:SJ cbx_stratix 2008:08:05:17:10:23:SJ cbx_stratixii 2008:08:07:13:54:47:SJ VERSION_END
//synthesis_resources = lut 6 reg 6
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"suppress_da_rule_internal=s102"} *)
module myfifo_a_graycounter2
(
aclr,
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