prev_cmp_vga.tan.qmsg

vga显示时序控制

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "CC\[4\] CC\[2\] CLK 89 ps " "Info: Found hold time violation between source  pin or register \"CC\[4\]\" and destination pin or register \"CC\[2\]\" for clock \"CLK\" (Hold time is 89 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.918 ns + Largest " "Info: + Largest clock skew is 0.918 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 6.769 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 6.769 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLK 1 CLK PIN_M1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 2; CLK Node = 'CLK'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.045 ns) + CELL(0.879 ns) 2.950 ns FS\[3\] 2 REG LCFF_X4_Y10_N17 7 " "Info: 2: + IC(1.045 ns) + CELL(0.879 ns) = 2.950 ns; Loc. = LCFF_X4_Y10_N17; Fanout = 7; REG Node = 'FS\[3\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.924 ns" { CLK FS[3] } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.228 ns) + CELL(0.000 ns) 5.178 ns FS\[3\]~clkctrl 3 COMB CLKCTRL_G12 4 " "Info: 3: + IC(2.228 ns) + CELL(0.000 ns) = 5.178 ns; Loc. = CLKCTRL_G12; Fanout = 4; COMB Node = 'FS\[3\]~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.228 ns" { FS[3] FS[3]~clkctrl } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.989 ns) + CELL(0.602 ns) 6.769 ns CC\[2\] 4 REG LCFF_X49_Y14_N15 8 " "Info: 4: + IC(0.989 ns) + CELL(0.602 ns) = 6.769 ns; Loc. = LCFF_X49_Y14_N15; Fanout = 8; REG Node = 'CC\[2\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.591 ns" { FS[3]~clkctrl CC[2] } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 37.04 % ) " "Info: Total cell delay = 2.507 ns ( 37.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.262 ns ( 62.96 % ) " "Info: Total interconnect delay = 4.262 ns ( 62.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.769 ns" { CLK FS[3] FS[3]~clkctrl CC[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.769 ns" { CLK {} CLK~combout {} FS[3] {} FS[3]~clkctrl {} CC[2] {} } { 0.000ns 0.000ns 1.045ns 2.228ns 0.989ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 5.851 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to source register is 5.851 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLK 1 CLK PIN_M1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 2; CLK Node = 'CLK'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.045 ns) + CELL(0.879 ns) 2.950 ns FS\[3\] 2 REG LCFF_X4_Y10_N17 7 " "Info: 2: + IC(1.045 ns) + CELL(0.879 ns) = 2.950 ns; Loc. = LCFF_X4_Y10_N17; Fanout = 7; REG Node = 'FS\[3\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.924 ns" { CLK FS[3] } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.299 ns) + CELL(0.602 ns) 5.851 ns CC\[4\] 3 REG LCFF_X49_Y14_N17 13 " "Info: 3: + IC(2.299 ns) + CELL(0.602 ns) = 5.851 ns; Loc. = LCFF_X49_Y14_N17; Fanout = 13; REG Node = 'CC\[4\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.901 ns" { FS[3] CC[4] } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 42.85 % ) " "Info: Total cell delay = 2.507 ns ( 42.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.344 ns ( 57.15 % ) " "Info: Total interconnect delay = 3.344 ns ( 57.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.851 ns" { CLK FS[3] CC[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.851 ns" { CLK {} CLK~combout {} FS[3] {} CC[4] {} } { 0.000ns 0.000ns 1.045ns 2.299ns } { 0.000ns 1.026ns 0.879ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.769 ns" { CLK FS[3] FS[3]~clkctrl CC[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.769 ns" { CLK {} CLK~combout {} FS[3] {} FS[3]~clkctrl {} CC[2] {} } { 0.000ns 0.000ns 1.045ns 2.228ns 0.989ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.851 ns" { CLK FS[3] CC[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.851 ns" { CLK {} CLK~combout {} FS[3] {} CC[4] {} } { 0.000ns 0.000ns 1.045ns 2.299ns } { 0.000ns 1.026ns 0.879ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns - " "Info: - Micro clock to output delay of source is 0.277 ns" {  } { { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 49 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.838 ns - Shortest register register " "Info: - Shortest register to register delay is 0.838 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CC\[4\] 1 REG LCFF_X49_Y14_N17 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X49_Y14_N17; Fanout = 13; REG Node = 'CC\[4\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CC[4] } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.420 ns) + CELL(0.322 ns) 0.742 ns CC~219 2 COMB LCCOMB_X49_Y14_N14 1 " "Info: 2: + IC(0.420 ns) + CELL(0.322 ns) = 0.742 ns; Loc. = LCCOMB_X49_Y14_N14; Fanout = 1; COMB Node = 'CC~219'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.742 ns" { CC[4] CC~219 } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 0.838 ns CC\[2\] 3 REG LCFF_X49_Y14_N15 8 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 0.838 ns; Loc. = LCFF_X49_Y14_N15; Fanout = 8; REG Node = 'CC\[2\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { CC~219 CC[2] } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.418 ns ( 49.88 % ) " "Info: Total cell delay = 0.418 ns ( 49.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.420 ns ( 50.12 % ) " "Info: Total interconnect delay = 0.420 ns ( 50.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.838 ns" { CC[4] CC~219 CC[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "0.838 ns" { CC[4] {} CC~219 {} CC[2] {} } { 0.000ns 0.420ns 0.000ns } { 0.000ns 0.322ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 49 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.769 ns" { CLK FS[3] FS[3]~clkctrl CC[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.769 ns" { CLK {} CLK~combout {} FS[3] {} FS[3]~clkctrl {} CC[2] {} } { 0.000ns 0.000ns 1.045ns 2.228ns 0.989ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.851 ns" { CLK FS[3] CC[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.851 ns" { CLK {} CLK~combout {} FS[3] {} CC[4] {} } { 0.000ns 0.000ns 1.045ns 2.299ns } { 0.000ns 1.026ns 0.879ns 0.602ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.838 ns" { CC[4] CC~219 CC[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "0.838 ns" { CC[4] {} CC~219 {} CC[2] {} } { 0.000ns 0.420ns 0.000ns } { 0.000ns 0.322ns 0.096ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK B LL\[2\] 20.941 ns register " "Info: tco from clock \"CLK\" to destination pin \"B\" through register \"LL\[2\]\" is 20.941 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 8.440 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 8.440 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLK 1 CLK PIN_M1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 2; CLK Node = 'CLK'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.045 ns) + CELL(0.879 ns) 2.950 ns FS\[3\] 2 REG LCFF_X4_Y10_N17 7 " "Info: 2: + IC(1.045 ns) + CELL(0.879 ns) = 2.950 ns; Loc. = LCFF_X4_Y10_N17; Fanout = 7; REG Node = 'FS\[3\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.924 ns" { CLK FS[3] } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.299 ns) + CELL(0.879 ns) 6.128 ns CC\[4\] 3 REG LCFF_X49_Y14_N17 13 " "Info: 3: + IC(2.299 ns) + CELL(0.879 ns) = 6.128 ns; Loc. = LCFF_X49_Y14_N17; Fanout = 13; REG Node = 'CC\[4\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.178 ns" { FS[3] CC[4] } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.716 ns) + CELL(0.000 ns) 6.844 ns CC\[4\]~clkctrl 4 COMB CLKCTRL_G7 9 " "Info: 4: + IC(0.716 ns) + CELL(0.000 ns) = 6.844 ns; Loc. = CLKCTRL_G7; Fanout = 9; COMB Node = 'CC\[4\]~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.716 ns" { CC[4] CC[4]~clkctrl } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.994 ns) + CELL(0.602 ns) 8.440 ns LL\[2\] 5 REG LCFF_X47_Y21_N7 6 " "Info: 5: + IC(0.994 ns) + CELL(0.602 ns) = 8.440 ns; Loc. = LCFF_X47_Y21_N7; Fanout = 6; REG Node = 'LL\[2\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.596 ns" { CC[4]~clkctrl LL[2] } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.386 ns ( 40.12 % ) " "Info: Total cell delay = 3.386 ns ( 40.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.054 ns ( 59.88 % ) " "Info: Total interconnect delay = 5.054 ns ( 59.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.440 ns" { CLK FS[3] CC[4] CC[4]~clkctrl LL[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.440 ns" { CLK {} CLK~combout {} FS[3] {} CC[4] {} CC[4]~clkctrl {} LL[2] {} } { 0.000ns 0.000ns 1.045ns 2.299ns 0.716ns 0.994ns } { 0.000ns 1.026ns 0.879ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 56 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.224 ns + Longest register pin " "Info: + Longest register to pin delay is 12.224 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LL\[2\] 1 REG LCFF_X47_Y21_N7 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X47_Y21_N7; Fanout = 6; REG Node = 'LL\[2\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { LL[2] } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.973 ns) + CELL(0.542 ns) 1.515 ns GRB~1834 2 COMB LCCOMB_X47_Y23_N28 1 " "Info: 2: + IC(0.973 ns) + CELL(0.542 ns) = 1.515 ns; Loc. = LCCOMB_X47_Y23_N28; Fanout = 1; COMB Node = 'GRB~1834'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.515 ns" { LL[2] GRB~1834 } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.289 ns) + CELL(0.521 ns) 2.325 ns GRB~1842 3 COMB LCCOMB_X47_Y23_N24 1 " "Info: 3: + IC(0.289 ns) + CELL(0.521 ns) = 2.325 ns; Loc. = LCCOMB_X47_Y23_N24; Fanout = 1; COMB Node = 'GRB~1842'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.810 ns" { GRB~1834 GRB~1842 } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.904 ns) + CELL(0.545 ns) 3.774 ns GRB~1835 4 COMB LCCOMB_X47_Y20_N8 1 " "Info: 4: + IC(0.904 ns) + CELL(0.545 ns) = 3.774 ns; Loc. = LCCOMB_X47_Y20_N8; Fanout = 1; COMB Node = 'GRB~1835'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.449 ns" { GRB~1842 GRB~1835 } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.303 ns) + CELL(0.322 ns) 4.399 ns GRB~1837 5 COMB LCCOMB_X47_Y20_N26 1 " "Info: 5: + IC(0.303 ns) + CELL(0.322 ns) = 4.399 ns; Loc. = LCCOMB_X47_Y20_N26; Fanout = 1; COMB Node = 'GRB~1837'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.625 ns" { GRB~1835 GRB~1837 } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.304 ns) + CELL(0.178 ns) 4.881 ns GRB~1843 6 COMB LCCOMB_X47_Y20_N14 1 " "Info: 6: + IC(0.304 ns) + CELL(0.178 ns) = 4.881 ns; Loc. = LCCOMB_X47_Y20_N14; Fanout = 1; COMB Node = 'GRB~1843'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.482 ns" { GRB~1837 GRB~1843 } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.303 ns) + CELL(0.322 ns) 5.506 ns GRB~1841 7 COMB LCCOMB_X47_Y20_N20 1 " "Info: 7: + IC(0.303 ns) + CELL(0.322 ns) = 5.506 ns; Loc. = LCCOMB_X47_Y20_N20; Fanout = 1; COMB Node = 'GRB~1841'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.625 ns" { GRB~1843 GRB~1841 } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.868 ns) + CELL(2.850 ns) 12.224 ns B 8 PIN PIN_F1 0 " "Info: 8: + IC(3.868 ns) + CELL(2.850 ns) = 12.224 ns; Loc. = PIN_F1; Fanout = 0; PIN Node = 'B'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.718 ns" { GRB~1841 B } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.280 ns ( 43.19 % ) " "Info: Total cell delay = 5.280 ns ( 43.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.944 ns ( 56.81 % ) " "Info: Total interconnect delay = 6.944 ns ( 56.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "12.224 ns" { LL[2] GRB~1834 GRB~1842 GRB~1835 GRB~1837 GRB~1843 GRB~1841 B } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "12.224 ns" { LL[2] {} GRB~1834 {} GRB~1842 {} GRB~1835 {} GRB~1837 {} GRB~1843 {} GRB~1841 {} B {} } { 0.000ns 0.973ns 0.289ns 0.904ns 0.303ns 0.304ns 0.303ns 3.868ns } { 0.000ns 0.542ns 0.521ns 0.545ns 0.322ns 0.178ns 0.322ns 2.850ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.440 ns" { CLK FS[3] CC[4] CC[4]~clkctrl LL[2] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.440 ns" { CLK {} CLK~combout {} FS[3] {} CC[4] {} CC[4]~clkctrl {} LL[2] {} } { 0.000ns 0.000ns 1.045ns 2.299ns 0.716ns 0.994ns } { 0.000ns 1.026ns 0.879ns 0.879ns 0.000ns 0.602ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "12.224 ns" { LL[2] GRB~1834 GRB~1842 GRB~1835 GRB~1837 GRB~1843 GRB~1841 B } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "12.224 ns" { LL[2] {} GRB~1834 {} GRB~1842 {} GRB~1835 {} GRB~1837 {} GRB~1843 {} GRB~1841 {} B {} } { 0.000ns 0.973ns 0.289ns 0.904ns 0.303ns 0.304ns 0.303ns 3.868ns } { 0.000ns 0.542ns 0.521ns 0.545ns 0.322ns 0.178ns 0.322ns 2.850ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "MD B 10.923 ns Longest " "Info: Longest tpd from source pin \"MD\" to destination pin \"B\" is 10.923 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns MD 1 CLK PIN_M2 4 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M2; Fanout = 4; CLK Node = 'MD'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { MD } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.232 ns) + CELL(0.322 ns) 3.580 ns GRB~1843 2 COMB LCCOMB_X47_Y20_N14 1 " "Info: 2: + IC(2.232 ns) + CELL(0.322 ns) = 3.580 ns; Loc. = LCCOMB_X47_Y20_N14; Fanout = 1; COMB Node = 'GRB~1843'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.554 ns" { MD GRB~1843 } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.303 ns) + CELL(0.322 ns) 4.205 ns GRB~1841 3 COMB LCCOMB_X47_Y20_N20 1 " "Info: 3: + IC(0.303 ns) + CELL(0.322 ns) = 4.205 ns; Loc. = LCCOMB_X47_Y20_N20; Fanout = 1; COMB Node = 'GRB~1841'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.625 ns" { GRB~1843 GRB~1841 } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.868 ns) + CELL(2.850 ns) 10.923 ns B 4 PIN PIN_F1 0 " "Info: 4: + IC(3.868 ns) + CELL(2.850 ns) = 10.923 ns; Loc. = PIN_F1; Fanout = 0; PIN Node = 'B'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.718 ns" { GRB~1841 B } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.520 ns ( 41.38 % ) " "Info: Total cell delay = 4.520 ns ( 41.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.403 ns ( 58.62 % ) " "Info: Total interconnect delay = 6.403 ns ( 58.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "10.923 ns" { MD GRB~1843 GRB~1841 B } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "10.923 ns" { MD {} MD~combout {} GRB~1843 {} GRB~1841 {} B {} } { 0.000ns 0.000ns 2.232ns 0.303ns 3.868ns } { 0.000ns 1.026ns 0.322ns 0.322ns 2.850ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "126 " "Info: Peak virtual memory: 126 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 14 16:03:32 2009 " "Info: Processing ended: Sat Mar 14 16:03:32 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}