prev_cmp_vga.tan.qmsg

vga显示时序控制

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "CC\[4\] " "Info: Detected ripple clock \"CC\[4\]\" as buffer" {  } { { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 49 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "CC\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "FS\[3\] " "Info: Detected ripple clock \"FS\[3\]\" as buffer" {  } { { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 40 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "FS\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register CC\[0\] register CC\[4\] 302.02 MHz 3.311 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 302.02 MHz between source register \"CC\[0\]\" and destination register \"CC\[4\]\" (period= 3.311 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.154 ns + Longest register register " "Info: + Longest register to register delay is 2.154 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CC\[0\] 1 REG LCFF_X49_Y14_N19 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X49_Y14_N19; Fanout = 7; REG Node = 'CC\[0\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CC[0] } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.397 ns) + CELL(0.495 ns) 0.892 ns Add2~61 2 COMB LCCOMB_X49_Y14_N18 2 " "Info: 2: + IC(0.397 ns) + CELL(0.495 ns) = 0.892 ns; Loc. = LCCOMB_X49_Y14_N18; Fanout = 2; COMB Node = 'Add2~61'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.892 ns" { CC[0] Add2~61 } "NODE_NAME" } } { "d:/altera/80/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/80/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 0.972 ns Add2~63 3 COMB LCCOMB_X49_Y14_N20 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 0.972 ns; Loc. = LCCOMB_X49_Y14_N20; Fanout = 2; COMB Node = 'Add2~63'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add2~61 Add2~63 } "NODE_NAME" } } { "d:/altera/80/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/80/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.052 ns Add2~65 4 COMB LCCOMB_X49_Y14_N22 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.052 ns; Loc. = LCCOMB_X49_Y14_N22; Fanout = 2; COMB Node = 'Add2~65'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add2~63 Add2~65 } "NODE_NAME" } } { "d:/altera/80/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/80/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.132 ns Add2~67 5 COMB LCCOMB_X49_Y14_N24 1 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.132 ns; Loc. = LCCOMB_X49_Y14_N24; Fanout = 1; COMB Node = 'Add2~67'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add2~65 Add2~67 } "NODE_NAME" } } { "d:/altera/80/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/80/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 1.590 ns Add2~68 6 COMB LCCOMB_X49_Y14_N26 1 " "Info: 6: + IC(0.000 ns) + CELL(0.458 ns) = 1.590 ns; Loc. = LCCOMB_X49_Y14_N26; Fanout = 1; COMB Node = 'Add2~68'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Add2~67 Add2~68 } "NODE_NAME" } } { "d:/altera/80/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/80/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.290 ns) + CELL(0.178 ns) 2.058 ns CC~216 7 COMB LCCOMB_X49_Y14_N16 1 " "Info: 7: + IC(0.290 ns) + CELL(0.178 ns) = 2.058 ns; Loc. = LCCOMB_X49_Y14_N16; Fanout = 1; COMB Node = 'CC~216'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.468 ns" { Add2~68 CC~216 } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 2.154 ns CC\[4\] 8 REG LCFF_X49_Y14_N17 13 " "Info: 8: + IC(0.000 ns) + CELL(0.096 ns) = 2.154 ns; Loc. = LCFF_X49_Y14_N17; Fanout = 13; REG Node = 'CC\[4\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { CC~216 CC[4] } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.467 ns ( 68.11 % ) " "Info: Total cell delay = 1.467 ns ( 68.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.687 ns ( 31.89 % ) " "Info: Total interconnect delay = 0.687 ns ( 31.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.154 ns" { CC[0] Add2~61 Add2~63 Add2~65 Add2~67 Add2~68 CC~216 CC[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.154 ns" { CC[0] {} Add2~61 {} Add2~63 {} Add2~65 {} Add2~67 {} Add2~68 {} CC~216 {} CC[4] {} } { 0.000ns 0.397ns 0.000ns 0.000ns 0.000ns 0.000ns 0.290ns 0.000ns } { 0.000ns 0.495ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.918 ns - Smallest " "Info: - Smallest clock skew is -0.918 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.851 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 5.851 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLK 1 CLK PIN_M1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 2; CLK Node = 'CLK'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.045 ns) + CELL(0.879 ns) 2.950 ns FS\[3\] 2 REG LCFF_X4_Y10_N17 7 " "Info: 2: + IC(1.045 ns) + CELL(0.879 ns) = 2.950 ns; Loc. = LCFF_X4_Y10_N17; Fanout = 7; REG Node = 'FS\[3\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.924 ns" { CLK FS[3] } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.299 ns) + CELL(0.602 ns) 5.851 ns CC\[4\] 3 REG LCFF_X49_Y14_N17 13 " "Info: 3: + IC(2.299 ns) + CELL(0.602 ns) = 5.851 ns; Loc. = LCFF_X49_Y14_N17; Fanout = 13; REG Node = 'CC\[4\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.901 ns" { FS[3] CC[4] } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 42.85 % ) " "Info: Total cell delay = 2.507 ns ( 42.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.344 ns ( 57.15 % ) " "Info: Total interconnect delay = 3.344 ns ( 57.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.851 ns" { CLK FS[3] CC[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.851 ns" { CLK {} CLK~combout {} FS[3] {} CC[4] {} } { 0.000ns 0.000ns 1.045ns 2.299ns } { 0.000ns 1.026ns 0.879ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 6.769 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 6.769 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLK 1 CLK PIN_M1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 2; CLK Node = 'CLK'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.045 ns) + CELL(0.879 ns) 2.950 ns FS\[3\] 2 REG LCFF_X4_Y10_N17 7 " "Info: 2: + IC(1.045 ns) + CELL(0.879 ns) = 2.950 ns; Loc. = LCFF_X4_Y10_N17; Fanout = 7; REG Node = 'FS\[3\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.924 ns" { CLK FS[3] } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.228 ns) + CELL(0.000 ns) 5.178 ns FS\[3\]~clkctrl 3 COMB CLKCTRL_G12 4 " "Info: 3: + IC(2.228 ns) + CELL(0.000 ns) = 5.178 ns; Loc. = CLKCTRL_G12; Fanout = 4; COMB Node = 'FS\[3\]~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.228 ns" { FS[3] FS[3]~clkctrl } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.989 ns) + CELL(0.602 ns) 6.769 ns CC\[0\] 4 REG LCFF_X49_Y14_N19 7 " "Info: 4: + IC(0.989 ns) + CELL(0.602 ns) = 6.769 ns; Loc. = LCFF_X49_Y14_N19; Fanout = 7; REG Node = 'CC\[0\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.591 ns" { FS[3]~clkctrl CC[0] } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 37.04 % ) " "Info: Total cell delay = 2.507 ns ( 37.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.262 ns ( 62.96 % ) " "Info: Total interconnect delay = 4.262 ns ( 62.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.769 ns" { CLK FS[3] FS[3]~clkctrl CC[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.769 ns" { CLK {} CLK~combout {} FS[3] {} FS[3]~clkctrl {} CC[0] {} } { 0.000ns 0.000ns 1.045ns 2.228ns 0.989ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.851 ns" { CLK FS[3] CC[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.851 ns" { CLK {} CLK~combout {} FS[3] {} CC[4] {} } { 0.000ns 0.000ns 1.045ns 2.299ns } { 0.000ns 1.026ns 0.879ns 0.602ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.769 ns" { CLK FS[3] FS[3]~clkctrl CC[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.769 ns" { CLK {} CLK~combout {} FS[3] {} FS[3]~clkctrl {} CC[0] {} } { 0.000ns 0.000ns 1.045ns 2.228ns 0.989ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 49 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 49 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.154 ns" { CC[0] Add2~61 Add2~63 Add2~65 Add2~67 Add2~68 CC~216 CC[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.154 ns" { CC[0] {} Add2~61 {} Add2~63 {} Add2~65 {} Add2~67 {} Add2~68 {} CC~216 {} CC[4] {} } { 0.000ns 0.397ns 0.000ns 0.000ns 0.000ns 0.000ns 0.290ns 0.000ns } { 0.000ns 0.495ns 0.080ns 0.080ns 0.080ns 0.458ns 0.178ns 0.096ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.851 ns" { CLK FS[3] CC[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.851 ns" { CLK {} CLK~combout {} FS[3] {} CC[4] {} } { 0.000ns 0.000ns 1.045ns 2.299ns } { 0.000ns 1.026ns 0.879ns 0.602ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.769 ns" { CLK FS[3] FS[3]~clkctrl CC[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.769 ns" { CLK {} CLK~combout {} FS[3] {} FS[3]~clkctrl {} CC[0] {} } { 0.000ns 0.000ns 1.045ns 2.228ns 0.989ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "MD register register MMD\[0\] MMD\[1\] 380.08 MHz Internal " "Info: Clock \"MD\" Internal fmax is restricted to 380.08 MHz between source register \"MMD\[0\]\" and destination register \"MMD\[1\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.631 ns " "Info: fmax restricted to clock pin edge rate 2.631 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.670 ns + Longest register register " "Info: + Longest register to register delay is 0.670 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns MMD\[0\] 1 REG LCFF_X47_Y20_N19 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X47_Y20_N19; Fanout = 7; REG Node = 'MMD\[0\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { MMD[0] } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.396 ns) + CELL(0.178 ns) 0.574 ns MMD~36 2 COMB LCCOMB_X47_Y20_N28 1 " "Info: 2: + IC(0.396 ns) + CELL(0.178 ns) = 0.574 ns; Loc. = LCCOMB_X47_Y20_N28; Fanout = 1; COMB Node = 'MMD~36'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.574 ns" { MMD[0] MMD~36 } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 0.670 ns MMD\[1\] 3 REG LCFF_X47_Y20_N29 4 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 0.670 ns; Loc. = LCFF_X47_Y20_N29; Fanout = 4; REG Node = 'MMD\[1\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { MMD~36 MMD[1] } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.274 ns ( 40.90 % ) " "Info: Total cell delay = 0.274 ns ( 40.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.396 ns ( 59.10 % ) " "Info: Total interconnect delay = 0.396 ns ( 59.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.670 ns" { MMD[0] MMD~36 MMD[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "0.670 ns" { MMD[0] {} MMD~36 {} MMD[1] {} } { 0.000ns 0.396ns 0.000ns } { 0.000ns 0.178ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MD destination 2.840 ns + Shortest register " "Info: + Shortest clock path from clock \"MD\" to destination register is 2.840 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns MD 1 CLK PIN_M2 4 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M2; Fanout = 4; CLK Node = 'MD'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { MD } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.232 ns) + CELL(0.000 ns) 1.258 ns MD~clkctrl 2 COMB CLKCTRL_G1 2 " "Info: 2: + IC(0.232 ns) + CELL(0.000 ns) = 1.258 ns; Loc. = CLKCTRL_G1; Fanout = 2; COMB Node = 'MD~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.232 ns" { MD MD~clkctrl } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.602 ns) 2.840 ns MMD\[1\] 3 REG LCFF_X47_Y20_N29 4 " "Info: 3: + IC(0.980 ns) + CELL(0.602 ns) = 2.840 ns; Loc. = LCFF_X47_Y20_N29; Fanout = 4; REG Node = 'MMD\[1\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.582 ns" { MD~clkctrl MMD[1] } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 57.32 % ) " "Info: Total cell delay = 1.628 ns ( 57.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.212 ns ( 42.68 % ) " "Info: Total interconnect delay = 1.212 ns ( 42.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.840 ns" { MD MD~clkctrl MMD[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.840 ns" { MD {} MD~combout {} MD~clkctrl {} MMD[1] {} } { 0.000ns 0.000ns 0.232ns 0.980ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MD source 2.840 ns - Longest register " "Info: - Longest clock path from clock \"MD\" to source register is 2.840 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns MD 1 CLK PIN_M2 4 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M2; Fanout = 4; CLK Node = 'MD'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { MD } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.232 ns) + CELL(0.000 ns) 1.258 ns MD~clkctrl 2 COMB CLKCTRL_G1 2 " "Info: 2: + IC(0.232 ns) + CELL(0.000 ns) = 1.258 ns; Loc. = CLKCTRL_G1; Fanout = 2; COMB Node = 'MD~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.232 ns" { MD MD~clkctrl } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.602 ns) 2.840 ns MMD\[0\] 3 REG LCFF_X47_Y20_N19 7 " "Info: 3: + IC(0.980 ns) + CELL(0.602 ns) = 2.840 ns; Loc. = LCFF_X47_Y20_N19; Fanout = 7; REG Node = 'MMD\[0\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.582 ns" { MD~clkctrl MMD[0] } "NODE_NAME" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 57.32 % ) " "Info: Total cell delay = 1.628 ns ( 57.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.212 ns ( 42.68 % ) " "Info: Total interconnect delay = 1.212 ns ( 42.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.840 ns" { MD MD~clkctrl MMD[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.840 ns" { MD {} MD~combout {} MD~clkctrl {} MMD[0] {} } { 0.000ns 0.000ns 0.232ns 0.980ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.840 ns" { MD MD~clkctrl MMD[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.840 ns" { MD {} MD~combout {} MD~clkctrl {} MMD[1] {} } { 0.000ns 0.000ns 0.232ns 0.980ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.840 ns" { MD MD~clkctrl MMD[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.840 ns" { MD {} MD~combout {} MD~clkctrl {} MMD[0] {} } { 0.000ns 0.000ns 0.232ns 0.980ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 25 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 25 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.670 ns" { MMD[0] MMD~36 MMD[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "0.670 ns" { MMD[0] {} MMD~36 {} MMD[1] {} } { 0.000ns 0.396ns 0.000ns } { 0.000ns 0.178ns 0.096ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.840 ns" { MD MD~clkctrl MMD[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.840 ns" { MD {} MD~combout {} MD~clkctrl {} MMD[1] {} } { 0.000ns 0.000ns 0.232ns 0.980ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.840 ns" { MD MD~clkctrl MMD[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.840 ns" { MD {} MD~combout {} MD~clkctrl {} MMD[0] {} } { 0.000ns 0.000ns 0.232ns 0.980ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { MMD[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { MMD[1] {} } {  } {  } "" } } { "VGA.vhd" "" { Text "D:/fpga.vhdl.scnu/VGA/VGA.vhd" 25 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLK 1 " "Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock \"CLK\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0 0}