vga.tan.rpt

vga显示时序控制

; N/A   ; None         ; 10.671 ns  ; MMD[1] ; B      ; MD         ;
; N/A   ; None         ; 10.227 ns  ; MMD[0] ; R      ; MD         ;
; N/A   ; None         ; 9.897 ns   ; MMD[0] ; G      ; MD         ;
; N/A   ; None         ; 9.856 ns   ; MMD[1] ; R      ; MD         ;
; N/A   ; None         ; 9.526 ns   ; MMD[1] ; G      ; MD         ;
; N/A   ; None         ; 9.046 ns   ; FS[3]  ; FS1[3] ; CLK        ;
; N/A   ; None         ; 7.738 ns   ; FS[0]  ; FS1[0] ; CLK        ;
; N/A   ; None         ; 7.504 ns   ; FS[2]  ; FS1[2] ; CLK        ;
; N/A   ; None         ; 7.476 ns   ; FS[1]  ; FS1[1] ; CLK        ;
; N/A   ; None         ; 7.324 ns   ; FS[3]  ; FCLK1  ; CLK        ;
+-------+--------------+------------+--------+--------+------------+


+---------------------------------------------------------+
; tpd                                                     ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A   ; None              ; 10.022 ns       ; MD   ; B  ;
; N/A   ; None              ; 7.778 ns        ; MD   ; R  ;
; N/A   ; None              ; 7.563 ns        ; MD   ; G  ;
+-------+-------------------+-----------------+------+----+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Thu Mar 19 18:02:42 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off VGA -c VGA --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
    Info: Assuming node "MD" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "CC[4]" as buffer
    Info: Detected ripple clock "FS[3]" as buffer
Info: Clock "CLK" has Internal fmax of 334.45 MHz between source register "LL[0]" and destination register "LL[8]" (period= 2.99 ns)
    Info: + Longest register to register delay is 2.751 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X5_Y1_N9; Fanout = 8; REG Node = 'LL[0]'
        Info: 2: + IC(0.418 ns) + CELL(0.495 ns) = 0.913 ns; Loc. = LCCOMB_X5_Y1_N8; Fanout = 2; COMB Node = 'Add3~109'
        Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 0.993 ns; Loc. = LCCOMB_X5_Y1_N10; Fanout = 2; COMB Node = 'Add3~111'
        Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.073 ns; Loc. = LCCOMB_X5_Y1_N12; Fanout = 2; COMB Node = 'Add3~113'
        Info: 5: + IC(0.000 ns) + CELL(0.174 ns) = 1.247 ns; Loc. = LCCOMB_X5_Y1_N14; Fanout = 2; COMB Node = 'Add3~115'
        Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 1.327 ns; Loc. = LCCOMB_X5_Y1_N16; Fanout = 2; COMB Node = 'Add3~117'
        Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 1.407 ns; Loc. = LCCOMB_X5_Y1_N18; Fanout = 2; COMB Node = 'Add3~119'
        Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 1.487 ns; Loc. = LCCOMB_X5_Y1_N20; Fanout = 2; COMB Node = 'Add3~121'
        Info: 9: + IC(0.000 ns) + CELL(0.080 ns) = 1.567 ns; Loc. = LCCOMB_X5_Y1_N22; Fanout = 1; COMB Node = 'Add3~123'
        Info: 10: + IC(0.000 ns) + CELL(0.458 ns) = 2.025 ns; Loc. = LCCOMB_X5_Y1_N24; Fanout = 1; COMB Node = 'Add3~124'
        Info: 11: + IC(0.308 ns) + CELL(0.322 ns) = 2.655 ns; Loc. = LCCOMB_X5_Y1_N0; Fanout = 1; COMB Node = 'LL~397'
        Info: 12: + IC(0.000 ns) + CELL(0.096 ns) = 2.751 ns; Loc. = LCFF_X5_Y1_N1; Fanout = 8; REG Node = 'LL[8]'
        Info: Total cell delay = 2.025 ns ( 73.61 % )
        Info: Total interconnect delay = 0.726 ns ( 26.39 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 8.944 ns
            Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 2; CLK Node = 'CLK'
            Info: 2: + IC(1.048 ns) + CELL(0.879 ns) = 2.953 ns; Loc. = LCFF_X5_Y13_N9; Fanout = 7; REG Node = 'FS[3]'
            Info: 3: + IC(2.284 ns) + CELL(0.879 ns) = 6.116 ns; Loc. = LCFF_X23_Y23_N9; Fanout = 14; REG Node = 'CC[4]'
            Info: 4: + IC(1.232 ns) + CELL(0.000 ns) = 7.348 ns; Loc. = CLKCTRL_G8; Fanout = 9; COMB Node = 'CC[4]~clkctrl'
            Info: 5: + IC(0.994 ns) + CELL(0.602 ns) = 8.944 ns; Loc. = LCFF_X5_Y1_N1; Fanout = 8; REG Node = 'LL[8]'
            Info: Total cell delay = 3.386 ns ( 37.86 % )
            Info: Total interconnect delay = 5.558 ns ( 62.14 % )
        Info: - Longest clock path from clock "CLK" to source register is 8.944 ns
            Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 2; CLK Node = 'CLK'
            Info: 2: + IC(1.048 ns) + CELL(0.879 ns) = 2.953 ns; Loc. = LCFF_X5_Y13_N9; Fanout = 7; REG Node = 'FS[3]'
            Info: 3: + IC(2.284 ns) + CELL(0.879 ns) = 6.116 ns; Loc. = LCFF_X23_Y23_N9; Fanout = 14; REG Node = 'CC[4]'
            Info: 4: + IC(1.232 ns) + CELL(0.000 ns) = 7.348 ns; Loc. = CLKCTRL_G8; Fanout = 9; COMB Node = 'CC[4]~clkctrl'
            Info: 5: + IC(0.994 ns) + CELL(0.602 ns) = 8.944 ns; Loc. = LCFF_X5_Y1_N9; Fanout = 8; REG Node = 'LL[0]'
            Info: Total cell delay = 3.386 ns ( 37.86 % )
            Info: Total interconnect delay = 5.558 ns ( 62.14 % )
    Info: + Micro clock to output delay of source is 0.277 ns
    Info: + Micro setup delay of destination is -0.038 ns
Info: Clock "MD" Internal fmax is restricted to 380.08 MHz between source register "MMD[0]" and destination register "MMD[1]"
    Info: fmax restricted to clock pin edge rate 2.631 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.674 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X13_Y21_N3; Fanout = 7; REG Node = 'MMD[0]'
            Info: 2: + IC(0.400 ns) + CELL(0.178 ns) = 0.578 ns; Loc. = LCCOMB_X13_Y21_N28; Fanout = 1; COMB Node = 'MMD~36'
            Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 0.674 ns; Loc. = LCFF_X13_Y21_N29; Fanout = 4; REG Node = 'MMD[1]'
            Info: Total cell delay = 0.274 ns ( 40.65 % )
            Info: Total interconnect delay = 0.400 ns ( 59.35 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "MD" to destination register is 2.849 ns
                Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M2; Fanout = 4; CLK Node = 'MD'
                Info: 2: + IC(0.232 ns) + CELL(0.000 ns) = 1.258 ns; Loc. = CLKCTRL_G1; Fanout = 2; COMB Node = 'MD~clkctrl'
                Info: 3: + IC(0.989 ns) + CELL(0.602 ns) = 2.849 ns; Loc. = LCFF_X13_Y21_N29; Fanout = 4; REG Node = 'MMD[1]'
                Info: Total cell delay = 1.628 ns ( 57.14 % )
                Info: Total interconnect delay = 1.221 ns ( 42.86 % )
            Info: - Longest clock path from clock "MD" to source register is 2.849 ns
                Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M2; Fanout = 4; CLK Node = 'MD'
                Info: 2: + IC(0.232 ns) + CELL(0.000 ns) = 1.258 ns; Loc. = CLKCTRL_G1; Fanout = 2; COMB Node = 'MD~clkctrl'
                Info: 3: + IC(0.989 ns) + CELL(0.602 ns) = 2.849 ns; Loc. = LCFF_X13_Y21_N3; Fanout = 7; REG Node = 'MMD[0]'
                Info: Total cell delay = 1.628 ns ( 57.14 % )
                Info: Total interconnect delay = 1.221 ns ( 42.86 % )
        Info: + Micro clock to output delay of source is 0.277 ns
        Info: + Micro setup delay of destination is -0.038 ns
Info: tco from clock "CLK" to destination pin "B" through register "LL[7]" is 23.910 ns
    Info: + Longest clock path from clock "CLK" to source register is 8.944 ns
        Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M1; Fanout = 2; CLK Node = 'CLK'
        Info: 2: + IC(1.048 ns) + CELL(0.879 ns) = 2.953 ns; Loc. = LCFF_X5_Y13_N9; Fanout = 7; REG Node = 'FS[3]'
        Info: 3: + IC(2.284 ns) + CELL(0.879 ns) = 6.116 ns; Loc. = LCFF_X23_Y23_N9; Fanout = 14; REG Node = 'CC[4]'
        Info: 4: + IC(1.232 ns) + CELL(0.000 ns) = 7.348 ns; Loc. = CLKCTRL_G8; Fanout = 9; COMB Node = 'CC[4]~clkctrl'
        Info: 5: + IC(0.994 ns) + CELL(0.602 ns) = 8.944 ns; Loc. = LCFF_X5_Y1_N3; Fanout = 9; REG Node = 'LL[7]'
        Info: Total cell delay = 3.386 ns ( 37.86 % )
        Info: Total interconnect delay = 5.558 ns ( 62.14 % )
    Info: + Micro clock to output delay of source is 0.277 ns
    Info: + Longest register to pin delay is 14.689 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X5_Y1_N3; Fanout = 9; REG Node = 'LL[7]'
        Info: 2: + IC(3.640 ns) + CELL(0.545 ns) = 4.185 ns; Loc. = LCCOMB_X14_Y23_N12; Fanout = 1; COMB Node = 'GRB~1834'
        Info: 3: + IC(0.286 ns) + CELL(0.178 ns) = 4.649 ns; Loc. = LCCOMB_X14_Y23_N24; Fanout = 1; COMB Node = 'GRB~1842'
        Info: 4: + IC(0.853 ns) + CELL(0.521 ns) = 6.023 ns; Loc. = LCCOMB_X13_Y21_N0; Fanout = 1; COMB Node = 'GRB~1835'
        Info: 5: + IC(0.299 ns) + CELL(0.521 ns) = 6.843 ns; Loc. = LCCOMB_X13_Y21_N10; Fanout = 1; COMB Node = 'GRB~1837'
        Info: 6: + IC(0.312 ns) + CELL(0.545 ns) = 7.700 ns; Loc. = LCCOMB_X13_Y21_N14; Fanout = 1; COMB Node = 'GRB~1843'
        Info: 7: + IC(0.309 ns) + CELL(0.516 ns) = 8.525 ns; Loc. = LCCOMB_X13_Y21_N20; Fanout = 1; COMB Node = 'GRB~1841'
        Info: 8: + IC(3.314 ns) + CELL(2.850 ns) = 14.689 ns; Loc. = PIN_E21; Fanout = 0; PIN Node = 'B'
        Info: Total cell delay = 5.676 ns ( 38.64 % )
        Info: Total interconnect delay = 9.013 ns ( 61.36 % )
Info: Longest tpd from source pin "MD" to destination pin "B" is 10.022 ns
    Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M2; Fanout = 4; CLK Node = 'MD'
    Info: 2: + IC(1.685 ns) + CELL(0.322 ns) = 3.033 ns; Loc. = LCCOMB_X13_Y21_N14; Fanout = 1; COMB Node = 'GRB~1843'
    Info: 3: + IC(0.309 ns) + CELL(0.516 ns) = 3.858 ns; Loc. = LCCOMB_X13_Y21_N20; Fanout = 1; COMB Node = 'GRB~1841'
    Info: 4: + IC(3.314 ns) + CELL(2.850 ns) = 10.022 ns; Loc. = PIN_E21; Fanout = 0; PIN Node = 'B'
    Info: Total cell delay = 4.714 ns ( 47.04 % )
    Info: Total interconnect delay = 5.308 ns ( 52.96 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 126 megabytes
    Info: Processing ended: Thu Mar 19 18:02:44 2009
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01