bcd.tan.qmsg

FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。

{ "Info" "ITDB_FULL_TPD_RESULT" "a\[2\] c\[1\] 14.322 ns Longest " "Info: Longest tpd from source pin \"a\[2\]\" to destination pin \"c\[1\]\" is 14.322 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns a\[2\] 1 PIN PIN_235 4 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_235; Fanout = 4; PIN Node = 'a\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "bcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/二进制转BCD码/" "" "" { a[2] } "NODE_NAME" } "" } } { "bcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/二进制转BCD码/bcd.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.427 ns) + CELL(0.442 ns) 8.344 ns c_tmp\[0\]~212 2 COMB LC_X19_Y20_N2 1 " "Info: 2: + IC(6.427 ns) + CELL(0.442 ns) = 8.344 ns; Loc. = LC_X19_Y20_N2; Fanout = 1; COMB Node = 'c_tmp\[0\]~212'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "bcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/二进制转BCD码/" "" "6.869 ns" { a[2] c_tmp[0]~212 } "NODE_NAME" } "" } } { "bcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/二进制转BCD码/bcd.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.423 ns) + CELL(0.590 ns) 9.357 ns c_tmp\[0\]~214 3 COMB LC_X19_Y20_N4 7 " "Info: 3: + IC(0.423 ns) + CELL(0.590 ns) = 9.357 ns; Loc. = LC_X19_Y20_N4; Fanout = 7; COMB Node = 'c_tmp\[0\]~214'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "bcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/二进制转BCD码/" "" "1.013 ns" { c_tmp[0]~212 c_tmp[0]~214 } "NODE_NAME" } "" } } { "bcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/二进制转BCD码/bcd.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.863 ns) + CELL(0.114 ns) 10.334 ns reduce_or~130 4 COMB LC_X20_Y20_N2 1 " "Info: 4: + IC(0.863 ns) + CELL(0.114 ns) = 10.334 ns; Loc. = LC_X20_Y20_N2; Fanout = 1; COMB Node = 'reduce_or~130'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "bcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/二进制转BCD码/" "" "0.977 ns" { c_tmp[0]~214 reduce_or~130 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.880 ns) + CELL(2.108 ns) 14.322 ns c\[1\] 5 PIN PIN_197 0 " "Info: 5: + IC(1.880 ns) + CELL(2.108 ns) = 14.322 ns; Loc. = PIN_197; Fanout = 0; PIN Node = 'c\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "bcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/二进制转BCD码/" "" "3.988 ns" { reduce_or~130 c[1] } "NODE_NAME" } "" } } { "bcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/二进制转BCD码/bcd.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.729 ns ( 33.02 % ) " "Info: Total cell delay = 4.729 ns ( 33.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.593 ns ( 66.98 % ) " "Info: Total interconnect delay = 9.593 ns ( 66.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "bcd" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/二进制转BCD码/db/bcd.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/二进制转BCD码/" "" "14.322 ns" { a[2] c_tmp[0]~212 c_tmp[0]~214 reduce_or~130 c[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "14.322 ns" { a[2] a[2]~out0 c_tmp[0]~212 c_tmp[0]~214 reduce_or~130 c[1] } { 0.000ns 0.000ns 6.427ns 0.423ns 0.863ns 1.880ns } { 0.000ns 1.475ns 0.442ns 0.590ns 0.114ns 2.108ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 20 16:25:21 2006 " "Info: Processing ended: Fri Oct 20 16:25:21 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}