bcd.map.qmsg

FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 20 16:25:12 2006 " "Info: Processing started: Fri Oct 20 16:25:12 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off bcd -c bcd " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off bcd -c bcd" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bcd.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file bcd.v" { { "Info" "ISGN_ENTITY_NAME" "1 bcd " "Info: Found entity 1: bcd" {  } { { "bcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/二进制转BCD码/bcd.v" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "bcd " "Info: Elaborating entity \"bcd\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 20 bcd.v(26) " "Warning (10230): Verilog HDL assignment warning at bcd.v(26): truncated value with size 32 to match size of target (20)" {  } { { "bcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/二进制转BCD码/bcd.v" 26 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "code_data bcd.v(45) " "Warning (10235): Verilog HDL Always Construct warning at bcd.v(45): variable \"code_data\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "bcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/二进制转BCD码/bcd.v" 45 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "code_data bcd.v(47) " "Warning (10235): Verilog HDL Always Construct warning at bcd.v(47): variable \"code_data\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "bcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/二进制转BCD码/bcd.v" 47 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "bcd.v(43) " "Info (10264): Verilog HDL Case Statement information at bcd.v(43): all case item expressions in this case statement are onehot" {  } { { "bcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/二进制转BCD码/bcd.v" 43 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "c\[0\] VCC " "Warning: Pin \"c\[0\]\" stuck at VCC" {  } { { "bcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/二进制转BCD码/bcd.v" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "bcd.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/二进制转BCD码/bcd.v" 33 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "78 " "Info: Implemented 78 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "62 " "Info: Implemented 62 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 20 16:25:13 2006 " "Info: Processing ended: Fri Oct 20 16:25:13 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}