bcd.tan.rpt

FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。

; N/A   ; None              ; 13.705 ns       ; a[1] ; c[2] ;
; N/A   ; None              ; 13.703 ns       ; a[1] ; c[3] ;
; N/A   ; None              ; 13.699 ns       ; a[1] ; c[4] ;
; N/A   ; None              ; 13.687 ns       ; a[1] ; c[5] ;
; N/A   ; None              ; 13.592 ns       ; a[3] ; c[1] ;
; N/A   ; None              ; 13.402 ns       ; a[3] ; c[7] ;
; N/A   ; None              ; 13.377 ns       ; a[3] ; c[6] ;
; N/A   ; None              ; 13.280 ns       ; a[3] ; c[4] ;
; N/A   ; None              ; 13.272 ns       ; a[3] ; c[2] ;
; N/A   ; None              ; 13.266 ns       ; a[3] ; c[3] ;
; N/A   ; None              ; 13.266 ns       ; a[0] ; c[1] ;
; N/A   ; None              ; 13.264 ns       ; a[3] ; c[5] ;
; N/A   ; None              ; 13.075 ns       ; a[0] ; c[7] ;
; N/A   ; None              ; 13.070 ns       ; a[0] ; c[6] ;
; N/A   ; None              ; 12.959 ns       ; a[0] ; c[2] ;
; N/A   ; None              ; 12.957 ns       ; a[0] ; c[3] ;
; N/A   ; None              ; 12.953 ns       ; a[0] ; c[4] ;
; N/A   ; None              ; 12.941 ns       ; a[0] ; c[5] ;
+-------+-------------------+-----------------+------+------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Fri Oct 20 16:25:21 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off bcd -c bcd --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 208.29 MHz between source register "cnt[0]" and destination register "cnt[17]" (period= 4.801 ns)
    Info: + Longest register to register delay is 4.540 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y12_N9; Fanout = 4; REG Node = 'cnt[0]'
        Info: 2: + IC(0.530 ns) + CELL(0.590 ns) = 1.120 ns; Loc. = LC_X25_Y12_N2; Fanout = 1; COMB Node = 'rtl~155'
        Info: 3: + IC(1.544 ns) + CELL(0.292 ns) = 2.956 ns; Loc. = LC_X23_Y11_N7; Fanout = 4; COMB Node = 'rtl~0'
        Info: 4: + IC(1.106 ns) + CELL(0.478 ns) = 4.540 ns; Loc. = LC_X25_Y11_N2; Fanout = 4; REG Node = 'cnt[17]'
        Info: Total cell delay = 1.360 ns ( 29.96 % )
        Info: Total interconnect delay = 3.180 ns ( 70.04 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.942 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'clk'
            Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X25_Y11_N2; Fanout = 4; REG Node = 'cnt[17]'
            Info: Total cell delay = 2.180 ns ( 74.10 % )
            Info: Total interconnect delay = 0.762 ns ( 25.90 % )
        Info: - Longest clock path from clock "clk" to source register is 2.942 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'clk'
            Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X25_Y12_N9; Fanout = 4; REG Node = 'cnt[0]'
            Info: Total cell delay = 2.180 ns ( 74.10 % )
            Info: Total interconnect delay = 0.762 ns ( 25.90 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "c[1]" through register "en[1]~reg0" is 12.364 ns
    Info: + Longest clock path from clock "clk" to source register is 2.942 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 22; CLK Node = 'clk'
        Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X23_Y11_N1; Fanout = 4; REG Node = 'en[1]~reg0'
        Info: Total cell delay = 2.180 ns ( 74.10 % )
        Info: Total interconnect delay = 0.762 ns ( 25.90 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 9.198 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y11_N1; Fanout = 4; REG Node = 'en[1]~reg0'
        Info: 2: + IC(2.408 ns) + CELL(0.590 ns) = 2.998 ns; Loc. = LC_X19_Y20_N5; Fanout = 4; COMB Node = 'c_tmp[3]~213'
        Info: 3: + IC(0.794 ns) + CELL(0.292 ns) = 4.084 ns; Loc. = LC_X20_Y20_N6; Fanout = 7; COMB Node = 'c_tmp[1]~215'
        Info: 4: + IC(0.536 ns) + CELL(0.590 ns) = 5.210 ns; Loc. = LC_X20_Y20_N2; Fanout = 1; COMB Node = 'reduce_or~130'
        Info: 5: + IC(1.880 ns) + CELL(2.108 ns) = 9.198 ns; Loc. = PIN_197; Fanout = 0; PIN Node = 'c[1]'
        Info: Total cell delay = 3.580 ns ( 38.92 % )
        Info: Total interconnect delay = 5.618 ns ( 61.08 % )
Info: Longest tpd from source pin "a[2]" to destination pin "c[1]" is 14.322 ns
    Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_235; Fanout = 4; PIN Node = 'a[2]'
    Info: 2: + IC(6.427 ns) + CELL(0.442 ns) = 8.344 ns; Loc. = LC_X19_Y20_N2; Fanout = 1; COMB Node = 'c_tmp[0]~212'
    Info: 3: + IC(0.423 ns) + CELL(0.590 ns) = 9.357 ns; Loc. = LC_X19_Y20_N4; Fanout = 7; COMB Node = 'c_tmp[0]~214'
    Info: 4: + IC(0.863 ns) + CELL(0.114 ns) = 10.334 ns; Loc. = LC_X20_Y20_N2; Fanout = 1; COMB Node = 'reduce_or~130'
    Info: 5: + IC(1.880 ns) + CELL(2.108 ns) = 14.322 ns; Loc. = PIN_197; Fanout = 0; PIN Node = 'c[1]'
    Info: Total cell delay = 4.729 ns ( 33.02 % )
    Info: Total interconnect delay = 9.593 ns ( 66.98 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Oct 20 16:25:21 2006
    Info: Elapsed time: 00:00:00