state_machine.smp_dump.txt

来自「FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基」· 文本 代码 · 共 12 行

State Machine - |state_machine|state
Name state.state7 state.state1 state.state2 state.state3 state.state4 state.state5 state.state6 state.state0 
state.state0 0 0 0 0 0 0 0 0 
state.state6 0 0 0 0 0 0 1 1 
state.state5 0 0 0 0 0 1 0 1 
state.state4 0 0 0 0 1 0 0 1 
state.state3 0 0 0 1 0 0 0 1 
state.state2 0 0 1 0 0 0 0 1 
state.state1 0 1 0 0 0 0 0 1 
state.state7 1 0 0 0 0 0 0 1