state_machine.hif

FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。

Version 5.1 Build 176 10/26/2005 SJ Full Version
33
1707
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
# entity
state_machine
# storage
db|state_machine.(0).cnf
db|state_machine.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
state_machine.v
4ed2a64527559c5641f0a6cc71199e0
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
state0
000
PARAMETER_BIN
DEF
state1
001
PARAMETER_BIN
DEF
state2
010
PARAMETER_BIN
DEF
state3
011
PARAMETER_BIN
DEF
state4
100
PARAMETER_BIN
DEF
state5
101
PARAMETER_BIN
DEF
state6
110
PARAMETER_BIN
DEF
state7
111
PARAMETER_BIN
DEF
}
# hierarchies {
|
}
# end
# complete