state_machine.tan.summary

来自「FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基」· SUMMARY 代码 · 共 37 行

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.548 ns
From           : state.state1
To             : c[7]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 204.88 MHz ( period = 4.881 ns )
From           : cnt[4]
To             : state.state7
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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