state_machine.tan.rpt

FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。

; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; cnt[11] ; state.state4 ; clk        ; clk      ; None                        ; None                      ; 2.955 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; cnt[11] ; state.state0 ; clk        ; clk      ; None                        ; None                      ; 2.955 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; cnt[11] ; state.state1 ; clk        ; clk      ; None                        ; None                      ; 2.955 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; cnt[3]  ; cnt[23]      ; clk        ; clk      ; None                        ; None                      ; 2.846 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; cnt[3]  ; cnt[22]      ; clk        ; clk      ; None                        ; None                      ; 2.846 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; cnt[2]  ; cnt[23]      ; clk        ; clk      ; None                        ; None                      ; 2.770 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; cnt[2]  ; cnt[22]      ; clk        ; clk      ; None                        ; None                      ; 2.770 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; cnt[3]  ; cnt[21]      ; clk        ; clk      ; None                        ; None                      ; 2.769 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; cnt[3]  ; cnt[20]      ; clk        ; clk      ; None                        ; None                      ; 2.769 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; cnt[3]  ; cnt[19]      ; clk        ; clk      ; None                        ; None                      ; 2.769 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; cnt[3]  ; cnt[18]      ; clk        ; clk      ; None                        ; None                      ; 2.769 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;         ;              ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+---------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------+
; tco                                                                  ;
+-------+--------------+------------+--------------+------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To   ; From Clock ;
+-------+--------------+------------+--------------+------+------------+
; N/A   ; None         ; 8.548 ns   ; state.state1 ; c[7] ; clk        ;
; N/A   ; None         ; 8.439 ns   ; state.state4 ; c[7] ; clk        ;
; N/A   ; None         ; 8.299 ns   ; state.state6 ; c[6] ; clk        ;
; N/A   ; None         ; 8.109 ns   ; state.state7 ; c[4] ; clk        ;
; N/A   ; None         ; 8.086 ns   ; state.state0 ; c[1] ; clk        ;
; N/A   ; None         ; 8.047 ns   ; state.state1 ; c[4] ; clk        ;
; N/A   ; None         ; 8.039 ns   ; state.state5 ; c[6] ; clk        ;
; N/A   ; None         ; 7.861 ns   ; state.state6 ; c[3] ; clk        ;
; N/A   ; None         ; 7.850 ns   ; state.state4 ; c[2] ; clk        ;
; N/A   ; None         ; 7.786 ns   ; state.state1 ; c[1] ; clk        ;
; N/A   ; None         ; 7.774 ns   ; state.state0 ; c[2] ; clk        ;
; N/A   ; None         ; 7.738 ns   ; state.state0 ; c[3] ; clk        ;
; N/A   ; None         ; 7.732 ns   ; state.state5 ; c[2] ; clk        ;
; N/A   ; None         ; 7.283 ns   ; state.state4 ; c[4] ; clk        ;
; N/A   ; None         ; 7.279 ns   ; state.state7 ; c[1] ; clk        ;
; N/A   ; None         ; 6.971 ns   ; state.state2 ; c[3] ; clk        ;
; N/A   ; None         ; 6.967 ns   ; state.state6 ; c[2] ; clk        ;
; N/A   ; None         ; 6.641 ns   ; state.state2 ; c[5] ; clk        ;
+-------+--------------+------------+--------------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Fri Oct 20 16:36:39 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off state_machine -c state_machine --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 204.88 MHz between source register "cnt[4]" and destination register "state.state5" (period= 4.881 ns)
    Info: + Longest register to register delay is 4.620 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y20_N7; Fanout = 4; REG Node = 'cnt[4]'
        Info: 2: + IC(1.602 ns) + CELL(0.292 ns) = 1.894 ns; Loc. = LC_X23_Y19_N3; Fanout = 1; COMB Node = 'rtl~192'
        Info: 3: + IC(0.400 ns) + CELL(0.442 ns) = 2.736 ns; Loc. = LC_X23_Y19_N5; Fanout = 1; COMB Node = 'rtl~195'
        Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 3.032 ns; Loc. = LC_X23_Y19_N6; Fanout = 8; COMB Node = 'rtl~0'
        Info: 5: + IC(0.721 ns) + CELL(0.867 ns) = 4.620 ns; Loc. = LC_X24_Y19_N2; Fanout = 3; REG Node = 'state.state5'
        Info: Total cell delay = 1.715 ns ( 37.12 % )
        Info: Total interconnect delay = 2.905 ns ( 62.88 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.962 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'
            Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X24_Y19_N2; Fanout = 3; REG Node = 'state.state5'
            Info: Total cell delay = 2.180 ns ( 73.60 % )
            Info: Total interconnect delay = 0.782 ns ( 26.40 % )
        Info: - Longest clock path from clock "clk" to source register is 2.962 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'
            Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X22_Y20_N7; Fanout = 4; REG Node = 'cnt[4]'
            Info: Total cell delay = 2.180 ns ( 73.60 % )
            Info: Total interconnect delay = 0.782 ns ( 26.40 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "c[7]" through register "state.state1" is 8.548 ns
    Info: + Longest clock path from clock "clk" to source register is 2.962 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'
        Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X23_Y19_N2; Fanout = 4; REG Node = 'state.state1'
        Info: Total cell delay = 2.180 ns ( 73.60 % )
        Info: Total interconnect delay = 0.782 ns ( 26.40 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 5.362 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y19_N2; Fanout = 4; REG Node = 'state.state1'
        Info: 2: + IC(0.752 ns) + CELL(0.442 ns) = 1.194 ns; Loc. = LC_X24_Y19_N3; Fanout = 1; COMB Node = 'c~9'
        Info: 3: + IC(2.060 ns) + CELL(2.108 ns) = 5.362 ns; Loc. = PIN_215; Fanout = 0; PIN Node = 'c[7]'
        Info: Total cell delay = 2.550 ns ( 47.56 % )
        Info: Total interconnect delay = 2.812 ns ( 52.44 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Oct 20 16:36:40 2006
    Info: Elapsed time: 00:00:01