encode.map.eqn

FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。

-- Copyright (C) 1991-2005 Altera Corporation
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-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
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-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L19 is c_tmp~363
--operation mode is normal

A1L19 = a[7] # a[6] # a[5] # a[4];


--A1L20 is c_tmp~364
--operation mode is normal

A1L20 = !a[4] & (a[3] # a[2]);


--A1L21 is c_tmp~365
--operation mode is normal

A1L21 = a[7] # a[6] # !a[5] & A1L20;


--A1L22 is c_tmp~366
--operation mode is normal

A1L22 = !a[4] & (a[3] # a[1] & !a[2]);


--A1L23 is c_tmp~367
--operation mode is normal

A1L23 = a[7] # !a[6] & (a[5] # A1L22);


--A1L35 is reduce_or~517
--operation mode is normal

A1L35 = !a[8] & (A1L21 & (A1L23 # !A1L19) # !A1L21 & A1L23 & !A1L19);


--A1L36 is reduce_or~518
--operation mode is normal

A1L36 = !a[8] & (A1L23 # A1L19 & !A1L21);


--A1L37 is reduce_or~519
--operation mode is normal

A1L37 = a[8] # A1L21 & (!A1L23 # !A1L19) # !A1L21 & (A1L19 $ !A1L23);


--A1L38 is reduce_or~520
--operation mode is normal

A1L38 = !A1L21 & !a[8] & (A1L19 $ A1L23);


--A1L39 is reduce_or~521
--operation mode is normal

A1L39 = a[7] # a[8] # !a[6] & !a[5];


--A1L40 is reduce_or~522
--operation mode is normal

A1L40 = a[8] # !a[7] & (A1L33 # a[6]);


--A1L33 is reduce_or~490
--operation mode is normal

A1L33 = a[2] # a[3] # a[4] # a[5];


--A1L41 is reduce_or~523
--operation mode is normal

A1L41 = A1L34 & !a[6] & !a[7] & !a[5];


--A1L34 is reduce_or~505
--operation mode is normal

A1L34 = !a[8] & a[2] & !a[3] & !a[4];


--a[7] is a[7]
--operation mode is input

a[7] = INPUT();


--a[6] is a[6]
--operation mode is input

a[6] = INPUT();


--a[5] is a[5]
--operation mode is input

a[5] = INPUT();


--a[4] is a[4]
--operation mode is input

a[4] = INPUT();


--a[3] is a[3]
--operation mode is input

a[3] = INPUT();


--a[2] is a[2]
--operation mode is input

a[2] = INPUT();


--a[1] is a[1]
--operation mode is input

a[1] = INPUT();


--a[8] is a[8]
--operation mode is input

a[8] = INPUT();


--c[0] is c[0]
--operation mode is output

c[0] = OUTPUT(VCC);


--c[1] is c[1]
--operation mode is output

c[1] = OUTPUT(!A1L40);


--c[2] is c[2]
--operation mode is output

c[2] = OUTPUT(A1L35);


--c[3] is c[3]
--operation mode is output

c[3] = OUTPUT(A1L36);


--c[4] is c[4]
--operation mode is output

c[4] = OUTPUT(!A1L37);


--c[5] is c[5]
--operation mode is output

c[5] = OUTPUT(A1L41);


--c[6] is c[6]
--operation mode is output

c[6] = OUTPUT(!A1L39);


--c[7] is c[7]
--operation mode is output

c[7] = OUTPUT(A1L38);


--en[0] is en[0]
--operation mode is output

en[0] = OUTPUT(GND);


--en[1] is en[1]
--operation mode is output

en[1] = OUTPUT(VCC);


--en[2] is en[2]
--operation mode is output

en[2] = OUTPUT(VCC);


--en[3] is en[3]
--operation mode is output

en[3] = OUTPUT(VCC);


--en[4] is en[4]
--operation mode is output

en[4] = OUTPUT(VCC);


--en[5] is en[5]
--operation mode is output

en[5] = OUTPUT(VCC);


--en[6] is en[6]
--operation mode is output

en[6] = OUTPUT(VCC);


--en[7] is en[7]
--operation mode is output

en[7] = OUTPUT(VCC);