📄 encode.tan.rpt
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Timing Analyzer report for encode
Fri Oct 20 15:58:04 2006
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 14.409 ns ; a[3] ; c[3] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 14.409 ns ; a[3] ; c[3] ;
; N/A ; None ; 14.406 ns ; a[3] ; c[4] ;
; N/A ; None ; 14.405 ns ; a[3] ; c[2] ;
; N/A ; None ; 14.251 ns ; a[4] ; c[3] ;
; N/A ; None ; 14.248 ns ; a[4] ; c[4] ;
; N/A ; None ; 14.247 ns ; a[4] ; c[2] ;
; N/A ; None ; 13.679 ns ; a[7] ; c[3] ;
; N/A ; None ; 13.677 ns ; a[7] ; c[4] ;
; N/A ; None ; 13.674 ns ; a[7] ; c[2] ;
; N/A ; None ; 13.658 ns ; a[2] ; c[3] ;
; N/A ; None ; 13.655 ns ; a[2] ; c[4] ;
; N/A ; None ; 13.654 ns ; a[2] ; c[2] ;
; N/A ; None ; 13.628 ns ; a[3] ; c[7] ;
; N/A ; None ; 13.613 ns ; a[3] ; c[1] ;
; N/A ; None ; 13.552 ns ; a[3] ; c[5] ;
; N/A ; None ; 13.538 ns ; a[8] ; c[5] ;
; N/A ; None ; 13.470 ns ; a[4] ; c[7] ;
; N/A ; None ; 13.455 ns ; a[4] ; c[1] ;
; N/A ; None ; 13.428 ns ; a[1] ; c[3] ;
; N/A ; None ; 13.426 ns ; a[1] ; c[4] ;
; N/A ; None ; 13.423 ns ; a[1] ; c[2] ;
; N/A ; None ; 13.402 ns ; a[4] ; c[5] ;
; N/A ; None ; 13.284 ns ; a[5] ; c[1] ;
; N/A ; None ; 13.283 ns ; a[6] ; c[3] ;
; N/A ; None ; 13.281 ns ; a[6] ; c[4] ;
; N/A ; None ; 13.278 ns ; a[6] ; c[2] ;
; N/A ; None ; 13.181 ns ; a[5] ; c[3] ;
; N/A ; None ; 13.179 ns ; a[5] ; c[4] ;
; N/A ; None ; 13.176 ns ; a[5] ; c[2] ;
; N/A ; None ; 12.935 ns ; a[7] ; c[1] ;
; N/A ; None ; 12.898 ns ; a[7] ; c[7] ;
; N/A ; None ; 12.877 ns ; a[2] ; c[7] ;
; N/A ; None ; 12.859 ns ; a[2] ; c[1] ;
; N/A ; None ; 12.814 ns ; a[2] ; c[5] ;
; N/A ; None ; 12.782 ns ; a[8] ; c[1] ;
; N/A ; None ; 12.647 ns ; a[1] ; c[7] ;
; N/A ; None ; 12.502 ns ; a[6] ; c[7] ;
; N/A ; None ; 12.444 ns ; a[6] ; c[1] ;
; N/A ; None ; 12.400 ns ; a[5] ; c[7] ;
; N/A ; None ; 12.368 ns ; a[8] ; c[3] ;
; N/A ; None ; 12.362 ns ; a[8] ; c[4] ;
; N/A ; None ; 12.361 ns ; a[8] ; c[2] ;
; N/A ; None ; 12.304 ns ; a[7] ; c[5] ;
; N/A ; None ; 12.101 ns ; a[6] ; c[5] ;
; N/A ; None ; 12.091 ns ; a[5] ; c[5] ;
; N/A ; None ; 11.841 ns ; a[7] ; c[6] ;
; N/A ; None ; 11.586 ns ; a[8] ; c[7] ;
; N/A ; None ; 11.583 ns ; a[8] ; c[6] ;
; N/A ; None ; 11.355 ns ; a[6] ; c[6] ;
; N/A ; None ; 11.346 ns ; a[5] ; c[6] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Fri Oct 20 15:58:04 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off encode -c encode --timing_analysis_only
Info: Longest tpd from source pin "a[3]" to destination pin "c[3]" is 14.409 ns
Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_235; Fanout = 4; PIN Node = 'a[3]'
Info: 2: + IC(5.404 ns) + CELL(0.590 ns) = 7.469 ns; Loc. = LC_X6_Y20_N6; Fanout = 1; COMB Node = 'c_tmp~364'
Info: 3: + IC(0.688 ns) + CELL(0.590 ns) = 8.747 ns; Loc. = LC_X7_Y20_N5; Fanout = 4; COMB Node = 'c_tmp~365'
Info: 4: + IC(0.439 ns) + CELL(0.442 ns) = 9.628 ns; Loc. = LC_X7_Y20_N9; Fanout = 1; COMB Node = 'reduce_or~518'
Info: 5: + IC(2.673 ns) + CELL(2.108 ns) = 14.409 ns; Loc. = PIN_201; Fanout = 0; PIN Node = 'c[3]'
Info: Total cell delay = 5.205 ns ( 36.12 % )
Info: Total interconnect delay = 9.204 ns ( 63.88 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Fri Oct 20 15:58:04 2006
Info: Elapsed time: 00:00:00
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