sub.map.summary

来自「FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基」· SUMMARY 代码 · 共 11 行

Analysis & Synthesis Status : Successful - Fri Oct 20 16:33:54 2006
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : sub
Top-level Entity Name : sub
Family : Cyclone
Total logic elements : 11
Total pins : 24
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0