sub.map.eqn

FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。

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--A1L6 is add~26
--operation mode is arithmetic

A1L6 = b[0] $ a[0];

--A1L7 is add~28
--operation mode is arithmetic

A1L7 = CARRY(a[0] # !b[0]);


--A1L8 is add~31
--operation mode is arithmetic

A1L8_carry_eqn = A1L7;
A1L8 = b[1] $ a[1] $ !A1L8_carry_eqn;

--A1L9 is add~33
--operation mode is arithmetic

A1L9 = CARRY(b[1] & (!A1L7 # !a[1]) # !b[1] & !a[1] & !A1L7);


--A1L10 is add~36
--operation mode is arithmetic

A1L10_carry_eqn = A1L9;
A1L10 = b[2] $ a[2] $ A1L10_carry_eqn;

--A1L11 is add~38
--operation mode is arithmetic

A1L11 = CARRY(b[2] & a[2] & !A1L9 # !b[2] & (a[2] # !A1L9));


--A1L12 is add~41
--operation mode is normal

A1L12_carry_eqn = A1L11;
A1L12 = b[3] $ a[3] $ !A1L12_carry_eqn;


--A1L36 is reduce_or~35
--operation mode is normal

A1L36 = A1L6 & (A1L12 # A1L8 $ A1L10) # !A1L6 & (A1L8 # A1L10 $ A1L12);


--A1L37 is reduce_or~36
--operation mode is normal

A1L37 = A1L6 & (A1L12 $ (A1L8 # !A1L10)) # !A1L6 & A1L8 & !A1L10 & !A1L12;


--A1L38 is reduce_or~37
--operation mode is normal

A1L38 = A1L8 & A1L6 & (!A1L12) # !A1L8 & (A1L10 & (!A1L12) # !A1L10 & A1L6);


--A1L39 is reduce_or~38
--operation mode is normal

A1L39 = A1L6 & (A1L8 $ !A1L10) # !A1L6 & (A1L8 & !A1L10 & A1L12 # !A1L8 & A1L10 & !A1L12);


--A1L40 is reduce_or~39
--operation mode is normal

A1L40 = A1L10 & A1L12 & (A1L8 # !A1L6) # !A1L10 & !A1L6 & A1L8 & !A1L12;


--A1L41 is reduce_or~40
--operation mode is normal

A1L41 = A1L8 & (A1L6 & (A1L12) # !A1L6 & A1L10) # !A1L8 & A1L10 & (A1L6 $ A1L12);


--A1L42 is reduce_or~41
--operation mode is normal

A1L42 = A1L10 & !A1L8 & (A1L6 $ !A1L12) # !A1L10 & A1L6 & (A1L8 $ !A1L12);


--b[0] is b[0]
--operation mode is input

b[0] = INPUT();


--a[0] is a[0]
--operation mode is input

a[0] = INPUT();


--b[1] is b[1]
--operation mode is input

b[1] = INPUT();


--a[1] is a[1]
--operation mode is input

a[1] = INPUT();


--b[2] is b[2]
--operation mode is input

b[2] = INPUT();


--a[2] is a[2]
--operation mode is input

a[2] = INPUT();


--b[3] is b[3]
--operation mode is input

b[3] = INPUT();


--a[3] is a[3]
--operation mode is input

a[3] = INPUT();


--c[0] is c[0]
--operation mode is output

c[0] = OUTPUT(VCC);


--c[1] is c[1]
--operation mode is output

c[1] = OUTPUT(!A1L36);


--c[2] is c[2]
--operation mode is output

c[2] = OUTPUT(A1L37);


--c[3] is c[3]
--operation mode is output

c[3] = OUTPUT(A1L38);


--c[4] is c[4]
--operation mode is output

c[4] = OUTPUT(A1L39);


--c[5] is c[5]
--operation mode is output

c[5] = OUTPUT(A1L40);


--c[6] is c[6]
--operation mode is output

c[6] = OUTPUT(A1L41);


--c[7] is c[7]
--operation mode is output

c[7] = OUTPUT(A1L42);


--en[0] is en[0]
--operation mode is output

en[0] = OUTPUT(GND);


--en[1] is en[1]
--operation mode is output

en[1] = OUTPUT(VCC);


--en[2] is en[2]
--operation mode is output

en[2] = OUTPUT(VCC);


--en[3] is en[3]
--operation mode is output

en[3] = OUTPUT(VCC);


--en[4] is en[4]
--operation mode is output

en[4] = OUTPUT(VCC);


--en[5] is en[5]
--operation mode is output

en[5] = OUTPUT(VCC);


--en[6] is en[6]
--operation mode is output

en[6] = OUTPUT(VCC);


--en[7] is en[7]
--operation mode is output

en[7] = OUTPUT(VCC);