sub.hier_info

FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。

|sub
a[0] => add~0.IN8
a[1] => add~0.IN7
a[2] => add~0.IN6
a[3] => add~0.IN5
b[0] => add~0.IN4
b[1] => add~0.IN3
b[2] => add~0.IN2
b[3] => add~0.IN1
c[0] <= <VCC>
c[1] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
c[2] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
c[3] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
c[4] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
c[5] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
c[6] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
c[7] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
en[0] <= <GND>
en[1] <= <VCC>
en[2] <= <VCC>
en[3] <= <VCC>
en[4] <= <VCC>
en[5] <= <VCC>
en[6] <= <VCC>
en[7] <= <VCC>