sub.tan.qmsg

FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 20 16:34:01 2006 " "Info: Processing started: Fri Oct 20 16:34:01 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off sub -c sub --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sub -c sub --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "b\[2\] c\[1\] 15.000 ns Longest " "Info: Longest tpd from source pin \"b\[2\]\" to destination pin \"c\[1\]\" is 15.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns b\[2\] 1 PIN PIN_239 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_239; Fanout = 3; PIN Node = 'b\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sub" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/减法器/db/sub.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/减法器/" "" "" { b[2] } "NODE_NAME" } "" } } { "sub.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/减法器/sub.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.389 ns) + CELL(0.575 ns) 7.439 ns add~38COUT1_53 2 COMB LC_X5_Y20_N2 1 " "Info: 2: + IC(5.389 ns) + CELL(0.575 ns) = 7.439 ns; Loc. = LC_X5_Y20_N2; Fanout = 1; COMB Node = 'add~38COUT1_53'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sub" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/减法器/db/sub.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/减法器/" "" "5.964 ns" { b[2] add~38COUT1_53 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 8.047 ns add~41 3 COMB LC_X5_Y20_N3 7 " "Info: 3: + IC(0.000 ns) + CELL(0.608 ns) = 8.047 ns; Loc. = LC_X5_Y20_N3; Fanout = 7; COMB Node = 'add~41'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sub" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/减法器/db/sub.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/减法器/" "" "0.608 ns" { add~38COUT1_53 add~41 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.891 ns) + CELL(0.590 ns) 10.528 ns reduce_or~35 4 COMB LC_X16_Y20_N8 1 " "Info: 4: + IC(1.891 ns) + CELL(0.590 ns) = 10.528 ns; Loc. = LC_X16_Y20_N8; Fanout = 1; COMB Node = 'reduce_or~35'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sub" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/减法器/db/sub.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/减法器/" "" "2.481 ns" { add~41 reduce_or~35 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.364 ns) + CELL(2.108 ns) 15.000 ns c\[1\] 5 PIN PIN_197 0 " "Info: 5: + IC(2.364 ns) + CELL(2.108 ns) = 15.000 ns; Loc. = PIN_197; Fanout = 0; PIN Node = 'c\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sub" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/减法器/db/sub.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/减法器/" "" "4.472 ns" { reduce_or~35 c[1] } "NODE_NAME" } "" } } { "sub.v" "" { Text "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/减法器/sub.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.356 ns ( 35.71 % ) " "Info: Total cell delay = 5.356 ns ( 35.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.644 ns ( 64.29 % ) " "Info: Total interconnect delay = 9.644 ns ( 64.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "sub" "UNKNOWN" "V1" "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/减法器/db/sub.quartus_db" { Floorplan "E:/扬创开发板/Mars-EDA-P/EP1C12/示例程序/veriloge/基础实验/减法器/" "" "15.000 ns" { b[2] add~38COUT1_53 add~41 reduce_or~35 c[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "15.000 ns" { b[2] b[2]~out0 add~38COUT1_53 add~41 reduce_or~35 c[1] } { 0.000ns 0.000ns 5.389ns 0.000ns 1.891ns 2.364ns } { 0.000ns 1.475ns 0.575ns 0.608ns 0.590ns 2.108ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 20 16:34:01 2006 " "Info: Processing ended: Fri Oct 20 16:34:01 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}