📄 sub.tan.rpt
字号:
Timing Analyzer report for sub
Fri Oct 20 16:34:01 2006
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 15.000 ns ; b[2] ; c[1] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 15.000 ns ; b[2] ; c[1] ;
; N/A ; None ; 14.874 ns ; b[1] ; c[1] ;
; N/A ; None ; 14.794 ns ; a[0] ; c[1] ;
; N/A ; None ; 14.704 ns ; a[1] ; c[1] ;
; N/A ; None ; 14.686 ns ; b[2] ; c[4] ;
; N/A ; None ; 14.680 ns ; b[2] ; c[5] ;
; N/A ; None ; 14.676 ns ; b[2] ; c[3] ;
; N/A ; None ; 14.672 ns ; b[2] ; c[2] ;
; N/A ; None ; 14.623 ns ; b[0] ; c[1] ;
; N/A ; None ; 14.560 ns ; b[1] ; c[4] ;
; N/A ; None ; 14.554 ns ; b[1] ; c[5] ;
; N/A ; None ; 14.550 ns ; b[1] ; c[3] ;
; N/A ; None ; 14.546 ns ; b[1] ; c[2] ;
; N/A ; None ; 14.522 ns ; a[2] ; c[1] ;
; N/A ; None ; 14.480 ns ; a[0] ; c[4] ;
; N/A ; None ; 14.474 ns ; a[0] ; c[5] ;
; N/A ; None ; 14.470 ns ; a[0] ; c[3] ;
; N/A ; None ; 14.466 ns ; a[0] ; c[2] ;
; N/A ; None ; 14.390 ns ; a[1] ; c[4] ;
; N/A ; None ; 14.384 ns ; a[1] ; c[5] ;
; N/A ; None ; 14.380 ns ; a[1] ; c[3] ;
; N/A ; None ; 14.376 ns ; a[1] ; c[2] ;
; N/A ; None ; 14.309 ns ; b[0] ; c[4] ;
; N/A ; None ; 14.303 ns ; b[0] ; c[5] ;
; N/A ; None ; 14.299 ns ; b[0] ; c[3] ;
; N/A ; None ; 14.295 ns ; b[0] ; c[2] ;
; N/A ; None ; 14.208 ns ; a[2] ; c[4] ;
; N/A ; None ; 14.202 ns ; a[2] ; c[5] ;
; N/A ; None ; 14.198 ns ; a[2] ; c[3] ;
; N/A ; None ; 14.194 ns ; a[2] ; c[2] ;
; N/A ; None ; 14.187 ns ; b[3] ; c[1] ;
; N/A ; None ; 13.908 ns ; b[2] ; c[7] ;
; N/A ; None ; 13.896 ns ; b[2] ; c[6] ;
; N/A ; None ; 13.873 ns ; b[3] ; c[4] ;
; N/A ; None ; 13.867 ns ; b[3] ; c[5] ;
; N/A ; None ; 13.863 ns ; b[3] ; c[3] ;
; N/A ; None ; 13.859 ns ; b[3] ; c[2] ;
; N/A ; None ; 13.782 ns ; b[1] ; c[7] ;
; N/A ; None ; 13.770 ns ; b[1] ; c[6] ;
; N/A ; None ; 13.702 ns ; a[0] ; c[7] ;
; N/A ; None ; 13.690 ns ; a[0] ; c[6] ;
; N/A ; None ; 13.612 ns ; a[1] ; c[7] ;
; N/A ; None ; 13.600 ns ; a[1] ; c[6] ;
; N/A ; None ; 13.594 ns ; a[3] ; c[1] ;
; N/A ; None ; 13.531 ns ; b[0] ; c[7] ;
; N/A ; None ; 13.519 ns ; b[0] ; c[6] ;
; N/A ; None ; 13.430 ns ; a[2] ; c[7] ;
; N/A ; None ; 13.418 ns ; a[2] ; c[6] ;
; N/A ; None ; 13.280 ns ; a[3] ; c[4] ;
; N/A ; None ; 13.274 ns ; a[3] ; c[5] ;
; N/A ; None ; 13.270 ns ; a[3] ; c[3] ;
; N/A ; None ; 13.266 ns ; a[3] ; c[2] ;
; N/A ; None ; 13.095 ns ; b[3] ; c[7] ;
; N/A ; None ; 13.083 ns ; b[3] ; c[6] ;
; N/A ; None ; 12.502 ns ; a[3] ; c[7] ;
; N/A ; None ; 12.490 ns ; a[3] ; c[6] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Fri Oct 20 16:34:01 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sub -c sub --timing_analysis_only
Info: Longest tpd from source pin "b[2]" to destination pin "c[1]" is 15.000 ns
Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_239; Fanout = 3; PIN Node = 'b[2]'
Info: 2: + IC(5.389 ns) + CELL(0.575 ns) = 7.439 ns; Loc. = LC_X5_Y20_N2; Fanout = 1; COMB Node = 'add~38COUT1_53'
Info: 3: + IC(0.000 ns) + CELL(0.608 ns) = 8.047 ns; Loc. = LC_X5_Y20_N3; Fanout = 7; COMB Node = 'add~41'
Info: 4: + IC(1.891 ns) + CELL(0.590 ns) = 10.528 ns; Loc. = LC_X16_Y20_N8; Fanout = 1; COMB Node = 'reduce_or~35'
Info: 5: + IC(2.364 ns) + CELL(2.108 ns) = 15.000 ns; Loc. = PIN_197; Fanout = 0; PIN Node = 'c[1]'
Info: Total cell delay = 5.356 ns ( 35.71 % )
Info: Total interconnect delay = 9.644 ns ( 64.29 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Fri Oct 20 16:34:01 2006
Info: Elapsed time: 00:00:00
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -