sub.fit.summary

来自「FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基」· SUMMARY 代码 · 共 13 行

Fitter Status : Successful - Fri Oct 20 16:33:58 2006
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : sub
Top-level Entity Name : sub
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Final
Total logic elements : 11 / 5,980 ( < 1 % )
Total pins : 24 / 173 ( 14 % )
Total virtual pins : 0
Total memory bits : 0 / 92,160 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )