📄 add.tan.rpt
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Timing Analyzer report for add
Fri Oct 20 16:28:36 2006
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 14.742 ns ; b[1] ; c[1] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 14.742 ns ; b[1] ; c[1] ;
; N/A ; None ; 14.435 ns ; b[1] ; c[3] ;
; N/A ; None ; 14.429 ns ; b[1] ; c[4] ;
; N/A ; None ; 14.426 ns ; b[1] ; c[2] ;
; N/A ; None ; 14.416 ns ; b[1] ; c[5] ;
; N/A ; None ; 14.283 ns ; b[0] ; c[1] ;
; N/A ; None ; 14.246 ns ; a[1] ; c[1] ;
; N/A ; None ; 14.166 ns ; a[0] ; c[1] ;
; N/A ; None ; 13.976 ns ; b[0] ; c[3] ;
; N/A ; None ; 13.970 ns ; b[0] ; c[4] ;
; N/A ; None ; 13.967 ns ; b[0] ; c[2] ;
; N/A ; None ; 13.957 ns ; b[0] ; c[5] ;
; N/A ; None ; 13.939 ns ; a[1] ; c[3] ;
; N/A ; None ; 13.933 ns ; a[1] ; c[4] ;
; N/A ; None ; 13.930 ns ; a[1] ; c[2] ;
; N/A ; None ; 13.920 ns ; a[1] ; c[5] ;
; N/A ; None ; 13.859 ns ; a[0] ; c[3] ;
; N/A ; None ; 13.853 ns ; a[0] ; c[4] ;
; N/A ; None ; 13.850 ns ; a[0] ; c[2] ;
; N/A ; None ; 13.840 ns ; a[0] ; c[5] ;
; N/A ; None ; 13.663 ns ; b[1] ; c[7] ;
; N/A ; None ; 13.658 ns ; b[1] ; c[6] ;
; N/A ; None ; 13.581 ns ; b[2] ; c[1] ;
; N/A ; None ; 13.344 ns ; a[2] ; c[1] ;
; N/A ; None ; 13.274 ns ; b[2] ; c[3] ;
; N/A ; None ; 13.268 ns ; b[2] ; c[4] ;
; N/A ; None ; 13.265 ns ; b[2] ; c[2] ;
; N/A ; None ; 13.255 ns ; b[2] ; c[5] ;
; N/A ; None ; 13.204 ns ; b[0] ; c[7] ;
; N/A ; None ; 13.199 ns ; b[0] ; c[6] ;
; N/A ; None ; 13.167 ns ; a[1] ; c[7] ;
; N/A ; None ; 13.162 ns ; a[1] ; c[6] ;
; N/A ; None ; 13.087 ns ; a[0] ; c[7] ;
; N/A ; None ; 13.082 ns ; a[0] ; c[6] ;
; N/A ; None ; 13.037 ns ; a[2] ; c[3] ;
; N/A ; None ; 13.031 ns ; a[2] ; c[4] ;
; N/A ; None ; 13.028 ns ; a[2] ; c[2] ;
; N/A ; None ; 13.018 ns ; a[2] ; c[5] ;
; N/A ; None ; 12.502 ns ; b[2] ; c[7] ;
; N/A ; None ; 12.497 ns ; b[2] ; c[6] ;
; N/A ; None ; 12.265 ns ; a[2] ; c[7] ;
; N/A ; None ; 12.260 ns ; a[2] ; c[6] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Fri Oct 20 16:28:36 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off add -c add --timing_analysis_only
Info: Longest tpd from source pin "b[1]" to destination pin "c[1]" is 14.742 ns
Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_237; Fanout = 2; PIN Node = 'b[1]'
Info: 2: + IC(5.678 ns) + CELL(0.590 ns) = 7.743 ns; Loc. = LC_X9_Y20_N4; Fanout = 2; COMB Node = 'add~310'
Info: 3: + IC(1.492 ns) + CELL(0.114 ns) = 9.349 ns; Loc. = LC_X16_Y20_N5; Fanout = 7; COMB Node = 'add~311'
Info: 4: + IC(0.481 ns) + CELL(0.442 ns) = 10.272 ns; Loc. = LC_X16_Y20_N8; Fanout = 1; COMB Node = 'reduce_or~35'
Info: 5: + IC(2.362 ns) + CELL(2.108 ns) = 14.742 ns; Loc. = PIN_197; Fanout = 0; PIN Node = 'c[1]'
Info: Total cell delay = 4.729 ns ( 32.08 % )
Info: Total interconnect delay = 10.013 ns ( 67.92 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Fri Oct 20 16:28:36 2006
Info: Elapsed time: 00:00:01
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