add.fit.eqn

FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L5 is add~308 at LC_X9_Y20_N2
--operation mode is normal

A1L5 = a[0] $ b[0];


--A1L6 is add~309 at LC_X9_Y20_N5
--operation mode is normal

A1L6 = b[1] $ a[1] $ (a[0] & b[0]);


--A1L7 is add~310 at LC_X9_Y20_N4
--operation mode is normal

A1L7 = b[1] & (a[1] # a[0] & b[0]) # !b[1] & a[1] & a[0] & b[0];


--A1L8 is add~311 at LC_X16_Y20_N5
--operation mode is normal

A1L8 = a[2] $ b[2] $ A1L7;


--A1L9 is add~312 at LC_X16_Y20_N1
--operation mode is normal

A1L9 = a[2] & (b[2] # A1L7) # !a[2] & b[2] & A1L7;


--A1L32 is reduce_or~35 at LC_X16_Y20_N8
--operation mode is normal

A1L32 = A1L5 & (A1L9 # A1L6 $ A1L8) # !A1L5 & (A1L6 # A1L8 $ A1L9);


--A1L33 is reduce_or~36 at LC_X16_Y20_N7
--operation mode is normal

A1L33 = A1L6 & !A1L9 & (A1L5 # !A1L8) # !A1L6 & A1L5 & (A1L8 $ !A1L9);


--A1L34 is reduce_or~37 at LC_X16_Y20_N2
--operation mode is normal

A1L34 = A1L6 & (A1L5 & !A1L9) # !A1L6 & (A1L8 & (!A1L9) # !A1L8 & A1L5);


--A1L35 is reduce_or~38 at LC_X16_Y20_N4
--operation mode is normal

A1L35 = A1L5 & (A1L6 $ !A1L8) # !A1L5 & (A1L6 & !A1L8 & A1L9 # !A1L6 & A1L8 & !A1L9);


--A1L36 is reduce_or~39 at LC_X16_Y20_N3
--operation mode is normal

A1L36 = A1L8 & A1L9 & (A1L6 # !A1L5) # !A1L8 & A1L6 & !A1L5 & !A1L9;


--A1L37 is reduce_or~40 at LC_X16_Y20_N6
--operation mode is normal

A1L37 = A1L6 & (A1L5 & (A1L9) # !A1L5 & A1L8) # !A1L6 & A1L8 & (A1L5 $ A1L9);


--A1L38 is reduce_or~41 at LC_X16_Y20_N9
--operation mode is normal

A1L38 = A1L8 & !A1L6 & (A1L5 $ !A1L9) # !A1L8 & A1L5 & (A1L6 $ !A1L9);


--b[0] is b[0] at PIN_236
--operation mode is input

b[0] = INPUT();


--a[0] is a[0] at PIN_233
--operation mode is input

a[0] = INPUT();


--a[1] is a[1] at PIN_234
--operation mode is input

a[1] = INPUT();


--b[1] is b[1] at PIN_237
--operation mode is input

b[1] = INPUT();


--a[2] is a[2] at PIN_235
--operation mode is input

a[2] = INPUT();


--b[2] is b[2] at PIN_238
--operation mode is input

b[2] = INPUT();


--c[0] is c[0] at PIN_194
--operation mode is output

c[0] = OUTPUT(VCC);


--c[1] is c[1] at PIN_197
--operation mode is output

c[1] = OUTPUT(!A1L32);


--c[2] is c[2] at PIN_200
--operation mode is output

c[2] = OUTPUT(A1L33);


--c[3] is c[3] at PIN_201
--operation mode is output

c[3] = OUTPUT(A1L34);


--c[4] is c[4] at PIN_202
--operation mode is output

c[4] = OUTPUT(A1L35);


--c[5] is c[5] at PIN_203
--operation mode is output

c[5] = OUTPUT(A1L36);


--c[6] is c[6] at PIN_214
--operation mode is output

c[6] = OUTPUT(A1L37);


--c[7] is c[7] at PIN_215
--operation mode is output

c[7] = OUTPUT(A1L38);


--en[0] is en[0] at PIN_193
--operation mode is output

en[0] = OUTPUT(GND);


--en[1] is en[1] at PIN_188
--operation mode is output

en[1] = OUTPUT(VCC);


--en[2] is en[2] at PIN_187
--operation mode is output

en[2] = OUTPUT(VCC);


--en[3] is en[3] at PIN_186
--operation mode is output

en[3] = OUTPUT(VCC);


--en[4] is en[4] at PIN_185
--operation mode is output

en[4] = OUTPUT(VCC);


--en[5] is en[5] at PIN_184
--operation mode is output

en[5] = OUTPUT(VCC);


--en[6] is en[6] at PIN_183
--operation mode is output

en[6] = OUTPUT(VCC);


--en[7] is en[7] at PIN_182
--operation mode is output

en[7] = OUTPUT(VCC);