mux.hier_info

FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。

|mux
a => d_tmp[3].OUTPUTSELECT
a => d_tmp[2].OUTPUTSELECT
a => d_tmp[1].OUTPUTSELECT
a => d_tmp[0].OUTPUTSELECT
b[0] => d_tmp[0].DATAB
b[1] => d_tmp[1].DATAB
b[2] => d_tmp[2].DATAB
b[3] => d_tmp[3].DATAB
c[0] => d_tmp[0].DATAA
c[1] => d_tmp[1].DATAA
c[2] => d_tmp[2].DATAA
c[3] => d_tmp[3].DATAA
d[0] <= <VCC>
d[1] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
d[2] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
d[3] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
d[4] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
d[5] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
d[6] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
d[7] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
en[0] <= <GND>
en[1] <= <VCC>
en[2] <= <VCC>
en[3] <= <VCC>
en[4] <= <VCC>
en[5] <= <VCC>
en[6] <= <VCC>
en[7] <= <VCC>