mux.fit.rpt

FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。

Fitter report for mux
Tue Dec 09 15:05:43 2008
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Equations
  6. Pin-Out File
  7. Fitter Resource Usage Summary
  8. Input Pins
  9. Output Pins
 10. I/O Bank Usage
 11. All Package Pins
 12. Migration Devices
 13. Output Pin Default Load For Reported TCO
 14. Fitter Resource Utilization by Entity
 15. Delay Chain Summary
 16. Pad To Core Delay Chain Fanout
 17. Non-Global High Fan-Out Signals
 18. Interconnect Usage Summary
 19. LAB Logic Elements
 20. LAB Signals Sourced
 21. LAB Signals Sourced Out
 22. LAB Distinct Inputs
 23. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------+
; Fitter Summary                                                   ;
+-----------------------+------------------------------------------+
; Fitter Status         ; Successful - Tue Dec 09 15:05:43 2008    ;
; Quartus II Version    ; 5.1 Build 176 10/26/2005 SJ Full Version ;
; Revision Name         ; mux                                      ;
; Top-level Entity Name ; mux                                      ;
; Family                ; Cyclone                                  ;
; Device                ; EP1C6Q240C8                              ;
; Timing Models         ; Final                                    ;
; Total logic elements  ; 11 / 5,980 ( < 1 % )                     ;
; Total pins            ; 25 / 173 ( 14 % )                        ;
; Total virtual pins    ; 0                                        ;
; Total memory bits     ; 0 / 92,160 ( 0 % )                       ;
; Total PLLs            ; 0 / 2 ( 0 % )                            ;
+-----------------------+------------------------------------------+


+------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                  ;
+------------------------------------------------------+--------------------------+--------------------------------+
; Option                                               ; Setting                  ; Default Value                  ;
+------------------------------------------------------+--------------------------+--------------------------------+
; Device                                               ; EP1C6Q240C8              ;                                ;
; Device Migration List                                ; EP1C6Q240C8,EP1C12Q240C8 ;                                ;
; Optimize Hold Timing                                 ; Off                      ; IO Paths and Minimum TPD Paths ;
; Fitter Effort                                        ; Standard Fit             ; Auto Fit                       ;
; SignalProbe signals routed during normal compilation ; Off                      ; Off                            ;
; Use smart compilation                                ; Off                      ; Off                            ;
; Router Timing Optimization Level                     ; Normal                   ; Normal                         ;
; Placement Effort Multiplier                          ; 1.0                      ; 1.0                            ;
; Router Effort Multiplier                             ; 1.0                      ; 1.0                            ;
; Optimize Fast-Corner Timing                          ; Off                      ; Off                            ;
; Optimize Timing                                      ; Normal compilation       ; Normal compilation             ;
; Optimize IOC Register Placement for Timing           ; On                       ; On                             ;
; Limit to One Fitting Attempt                         ; Off                      ; Off                            ;
; Final Placement Optimizations                        ; Automatically            ; Automatically                  ;
; Fitter Aggressive Routability Optimizations          ; Automatically            ; Automatically                  ;
; Fitter Initial Placement Seed                        ; 1                        ; 1                              ;
; Slow Slew Rate                                       ; Off                      ; Off                            ;
; PCI I/O                                              ; Off                      ; Off                            ;
; Weak Pull-Up Resistor                                ; Off                      ; Off                            ;
; Enable Bus-Hold Circuitry                            ; Off                      ; Off                            ;
; Auto Global Memory Control Signals                   ; Off                      ; Off                            ;