📄 mux.tan.rpt
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Timing Analyzer report for mux
Tue Dec 09 15:05:51 2008
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 13.844 ns ; b[3] ; d[1] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 13.844 ns ; b[3] ; d[1] ;
; N/A ; None ; 13.802 ns ; c[3] ; d[1] ;
; N/A ; None ; 13.720 ns ; a ; d[1] ;
; N/A ; None ; 13.675 ns ; c[1] ; d[1] ;
; N/A ; None ; 13.562 ns ; b[2] ; d[1] ;
; N/A ; None ; 13.556 ns ; b[3] ; d[4] ;
; N/A ; None ; 13.552 ns ; b[3] ; d[2] ;
; N/A ; None ; 13.551 ns ; b[3] ; d[3] ;
; N/A ; None ; 13.529 ns ; b[3] ; d[5] ;
; N/A ; None ; 13.520 ns ; c[2] ; d[1] ;
; N/A ; None ; 13.514 ns ; c[3] ; d[4] ;
; N/A ; None ; 13.510 ns ; c[3] ; d[2] ;
; N/A ; None ; 13.509 ns ; c[3] ; d[3] ;
; N/A ; None ; 13.487 ns ; c[3] ; d[5] ;
; N/A ; None ; 13.462 ns ; b[1] ; d[1] ;
; N/A ; None ; 13.432 ns ; a ; d[4] ;
; N/A ; None ; 13.428 ns ; a ; d[2] ;
; N/A ; None ; 13.427 ns ; a ; d[3] ;
; N/A ; None ; 13.405 ns ; a ; d[5] ;
; N/A ; None ; 13.386 ns ; c[1] ; d[2] ;
; N/A ; None ; 13.382 ns ; c[1] ; d[4] ;
; N/A ; None ; 13.382 ns ; c[1] ; d[3] ;
; N/A ; None ; 13.359 ns ; c[1] ; d[5] ;
; N/A ; None ; 13.273 ns ; b[2] ; d[2] ;
; N/A ; None ; 13.272 ns ; b[2] ; d[4] ;
; N/A ; None ; 13.265 ns ; b[2] ; d[3] ;
; N/A ; None ; 13.258 ns ; c[0] ; d[1] ;
; N/A ; None ; 13.243 ns ; b[2] ; d[5] ;
; N/A ; None ; 13.231 ns ; c[2] ; d[2] ;
; N/A ; None ; 13.230 ns ; c[2] ; d[4] ;
; N/A ; None ; 13.223 ns ; c[2] ; d[3] ;
; N/A ; None ; 13.201 ns ; c[2] ; d[5] ;
; N/A ; None ; 13.173 ns ; b[1] ; d[2] ;
; N/A ; None ; 13.169 ns ; b[1] ; d[4] ;
; N/A ; None ; 13.169 ns ; b[1] ; d[3] ;
; N/A ; None ; 13.146 ns ; b[1] ; d[5] ;
; N/A ; None ; 12.972 ns ; c[0] ; d[3] ;
; N/A ; None ; 12.971 ns ; c[0] ; d[4] ;
; N/A ; None ; 12.964 ns ; c[0] ; d[2] ;
; N/A ; None ; 12.949 ns ; c[0] ; d[5] ;
; N/A ; None ; 12.779 ns ; b[3] ; d[6] ;
; N/A ; None ; 12.775 ns ; b[3] ; d[7] ;
; N/A ; None ; 12.748 ns ; b[0] ; d[1] ;
; N/A ; None ; 12.737 ns ; c[3] ; d[6] ;
; N/A ; None ; 12.733 ns ; c[3] ; d[7] ;
; N/A ; None ; 12.655 ns ; a ; d[6] ;
; N/A ; None ; 12.651 ns ; a ; d[7] ;
; N/A ; None ; 12.609 ns ; c[1] ; d[6] ;
; N/A ; None ; 12.605 ns ; c[1] ; d[7] ;
; N/A ; None ; 12.496 ns ; b[2] ; d[6] ;
; N/A ; None ; 12.494 ns ; b[2] ; d[7] ;
; N/A ; None ; 12.462 ns ; b[0] ; d[3] ;
; N/A ; None ; 12.461 ns ; b[0] ; d[4] ;
; N/A ; None ; 12.454 ns ; c[2] ; d[6] ;
; N/A ; None ; 12.454 ns ; b[0] ; d[2] ;
; N/A ; None ; 12.452 ns ; c[2] ; d[7] ;
; N/A ; None ; 12.439 ns ; b[0] ; d[5] ;
; N/A ; None ; 12.396 ns ; b[1] ; d[6] ;
; N/A ; None ; 12.392 ns ; b[1] ; d[7] ;
; N/A ; None ; 12.198 ns ; c[0] ; d[6] ;
; N/A ; None ; 12.194 ns ; c[0] ; d[7] ;
; N/A ; None ; 11.688 ns ; b[0] ; d[6] ;
; N/A ; None ; 11.684 ns ; b[0] ; d[7] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Tue Dec 09 15:05:50 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mux -c mux --timing_analysis_only
Info: Longest tpd from source pin "b[3]" to destination pin "d[1]" is 13.844 ns
Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_236; Fanout = 1; PIN Node = 'b[3]'
Info: 2: + IC(5.037 ns) + CELL(0.442 ns) = 6.954 ns; Loc. = LC_X5_Y20_N4; Fanout = 7; COMB Node = 'd_tmp[3]~39'
Info: 3: + IC(1.232 ns) + CELL(0.590 ns) = 8.776 ns; Loc. = LC_X7_Y20_N2; Fanout = 1; COMB Node = 'reduce_or~35'
Info: 4: + IC(2.960 ns) + CELL(2.108 ns) = 13.844 ns; Loc. = PIN_197; Fanout = 0; PIN Node = 'd[1]'
Info: Total cell delay = 4.615 ns ( 33.34 % )
Info: Total interconnect delay = 9.229 ns ( 66.66 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Tue Dec 09 15:05:51 2008
Info: Elapsed time: 00:00:01
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