mlt.map.eqn

FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。

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-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
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-- without limitation, that your use is for the sole purpose of 
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-- applicable agreement for further details.
--A1L25 is reduce_or~35
--operation mode is normal

A1L25 = b[1] & (a[1] # a[0]) # !b[1] & a[1] & b[0];


--A1L26 is reduce_or~36
--operation mode is normal

A1L26 = b[1] & !a[1] & (a[0]) # !b[1] & b[0] & (a[1] # a[0]);


--A1L27 is reduce_or~37
--operation mode is normal

A1L27 = b[0] & (a[0]) # !b[0] & b[1] & a[1] & !a[0];


--A1L28 is reduce_or~38
--operation mode is normal

A1L28 = b[1] & a[1] & (b[0] $ !a[0]) # !b[1] & !a[1] & b[0] & a[0];


--A1L29 is reduce_or~39
--operation mode is normal

A1L29 = b[1] & !a[1] & !b[0] & a[0] # !b[1] & a[1] & b[0] & !a[0];


--A1L30 is reduce_or~40
--operation mode is normal

A1L30 = b[1] & a[1] & (b[0] $ a[0]);


--A1L31 is reduce_or~41
--operation mode is normal

A1L31 = b[1] & a[1] & !b[0] & !a[0] # !b[1] & !a[1] & b[0] & a[0];


--b[1] is b[1]
--operation mode is input

b[1] = INPUT();


--a[1] is a[1]
--operation mode is input

a[1] = INPUT();


--b[0] is b[0]
--operation mode is input

b[0] = INPUT();


--a[0] is a[0]
--operation mode is input

a[0] = INPUT();


--c[0] is c[0]
--operation mode is output

c[0] = OUTPUT(VCC);


--c[1] is c[1]
--operation mode is output

c[1] = OUTPUT(!A1L25);


--c[2] is c[2]
--operation mode is output

c[2] = OUTPUT(A1L26);


--c[3] is c[3]
--operation mode is output

c[3] = OUTPUT(A1L27);


--c[4] is c[4]
--operation mode is output

c[4] = OUTPUT(A1L28);


--c[5] is c[5]
--operation mode is output

c[5] = OUTPUT(A1L29);


--c[6] is c[6]
--operation mode is output

c[6] = OUTPUT(A1L30);


--c[7] is c[7]
--operation mode is output

c[7] = OUTPUT(A1L31);


--en[0] is en[0]
--operation mode is output

en[0] = OUTPUT(GND);


--en[1] is en[1]
--operation mode is output

en[1] = OUTPUT(VCC);


--en[2] is en[2]
--operation mode is output

en[2] = OUTPUT(VCC);


--en[3] is en[3]
--operation mode is output

en[3] = OUTPUT(VCC);


--en[4] is en[4]
--operation mode is output

en[4] = OUTPUT(VCC);


--en[5] is en[5]
--operation mode is output

en[5] = OUTPUT(VCC);


--en[6] is en[6]
--operation mode is output

en[6] = OUTPUT(VCC);


--en[7] is en[7]
--operation mode is output

en[7] = OUTPUT(VCC);