📄 div.tan.rpt
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Timing Analyzer report for div
Fri Oct 20 16:18:11 2006
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 15.612 ns ; b[2] ; c[2] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 15.612 ns ; b[2] ; c[2] ;
; N/A ; None ; 15.610 ns ; b[2] ; c[1] ;
; N/A ; None ; 15.601 ns ; b[2] ; c[4] ;
; N/A ; None ; 15.494 ns ; a[2] ; c[2] ;
; N/A ; None ; 15.492 ns ; a[2] ; c[1] ;
; N/A ; None ; 15.483 ns ; a[2] ; c[4] ;
; N/A ; None ; 15.295 ns ; b[2] ; c[3] ;
; N/A ; None ; 15.282 ns ; b[1] ; c[2] ;
; N/A ; None ; 15.280 ns ; b[1] ; c[1] ;
; N/A ; None ; 15.271 ns ; b[1] ; c[4] ;
; N/A ; None ; 15.177 ns ; a[2] ; c[3] ;
; N/A ; None ; 14.965 ns ; b[1] ; c[3] ;
; N/A ; None ; 14.933 ns ; a[0] ; c[2] ;
; N/A ; None ; 14.931 ns ; a[0] ; c[1] ;
; N/A ; None ; 14.922 ns ; a[0] ; c[4] ;
; N/A ; None ; 14.843 ns ; b[2] ; c[6] ;
; N/A ; None ; 14.840 ns ; b[2] ; c[7] ;
; N/A ; None ; 14.725 ns ; a[2] ; c[6] ;
; N/A ; None ; 14.722 ns ; a[2] ; c[7] ;
; N/A ; None ; 14.616 ns ; a[0] ; c[3] ;
; N/A ; None ; 14.513 ns ; b[1] ; c[6] ;
; N/A ; None ; 14.510 ns ; b[1] ; c[7] ;
; N/A ; None ; 14.164 ns ; a[0] ; c[6] ;
; N/A ; None ; 14.161 ns ; a[0] ; c[7] ;
; N/A ; None ; 13.962 ns ; b[0] ; c[2] ;
; N/A ; None ; 13.960 ns ; b[0] ; c[1] ;
; N/A ; None ; 13.951 ns ; b[0] ; c[4] ;
; N/A ; None ; 13.645 ns ; b[0] ; c[3] ;
; N/A ; None ; 13.464 ns ; a[1] ; c[2] ;
; N/A ; None ; 13.463 ns ; a[1] ; c[1] ;
; N/A ; None ; 13.453 ns ; a[1] ; c[4] ;
; N/A ; None ; 13.193 ns ; b[0] ; c[6] ;
; N/A ; None ; 13.190 ns ; b[0] ; c[7] ;
; N/A ; None ; 13.170 ns ; a[1] ; c[3] ;
; N/A ; None ; 13.110 ns ; b[1] ; c[5] ;
; N/A ; None ; 12.800 ns ; a[0] ; c[5] ;
; N/A ; None ; 12.694 ns ; a[1] ; c[6] ;
; N/A ; None ; 12.691 ns ; a[1] ; c[7] ;
; N/A ; None ; 12.686 ns ; a[1] ; c[5] ;
; N/A ; None ; 12.567 ns ; b[0] ; c[5] ;
; N/A ; None ; 12.424 ns ; b[2] ; c[5] ;
; N/A ; None ; 12.304 ns ; a[2] ; c[5] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Fri Oct 20 16:18:10 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off div -c div --timing_analysis_only
Info: Longest tpd from source pin "b[2]" to destination pin "c[2]" is 15.612 ns
Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_238; Fanout = 6; PIN Node = 'b[2]'
Info: 2: + IC(6.070 ns) + CELL(0.442 ns) = 7.987 ns; Loc. = LC_X12_Y20_N1; Fanout = 2; COMB Node = 'c_tmp[0]~454'
Info: 3: + IC(0.470 ns) + CELL(0.590 ns) = 9.047 ns; Loc. = LC_X12_Y20_N8; Fanout = 1; COMB Node = 'c_tmp[0]~456'
Info: 4: + IC(0.404 ns) + CELL(0.442 ns) = 9.893 ns; Loc. = LC_X12_Y20_N7; Fanout = 6; COMB Node = 'c_tmp[0]~458'
Info: 5: + IC(0.832 ns) + CELL(0.442 ns) = 11.167 ns; Loc. = LC_X13_Y20_N3; Fanout = 1; COMB Node = 'reduce_or~740'
Info: 6: + IC(2.337 ns) + CELL(2.108 ns) = 15.612 ns; Loc. = PIN_200; Fanout = 0; PIN Node = 'c[2]'
Info: Total cell delay = 5.499 ns ( 35.22 % )
Info: Total interconnect delay = 10.113 ns ( 64.78 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Fri Oct 20 16:18:11 2006
Info: Elapsed time: 00:00:01
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