div.flow.rpt

FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。

Flow report for div
Fri Oct 20 16:18:11 2006
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Elapsed Time
  5. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------+
; Flow Summary                                                       ;
+-------------------------+------------------------------------------+
; Flow Status             ; Successful - Fri Oct 20 16:18:11 2006    ;
; Quartus II Version      ; 5.1 Build 176 10/26/2005 SJ Full Version ;
; Revision Name           ; div                                      ;
; Top-level Entity Name   ; div                                      ;
; Family                  ; Cyclone                                  ;
; Device                  ; EP1C6Q240C8                              ;
; Timing Models           ; Final                                    ;
; Met timing requirements ; Yes                                      ;
; Total logic elements    ; 18 / 5,980 ( < 1 % )                     ;
; Total pins              ; 22 / 185 ( 12 % )                        ;
; Total virtual pins      ; 0                                        ;
; Total memory bits       ; 0 / 92,160 ( 0 % )                       ;
; Total PLLs              ; 0 / 2 ( 0 % )                            ;
+-------------------------+------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 10/20/2006 16:18:03 ;
; Main task         ; Compilation         ;
; Revision Name     ; div                 ;
+-------------------+---------------------+


+-------------------------------------+
; Flow Elapsed Time                   ;
+----------------------+--------------+
; Module Name          ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:01     ;
; Fitter               ; 00:00:03     ;
; Assembler            ; 00:00:01     ;
; Timing Analyzer      ; 00:00:01     ;
; Total                ; 00:00:06     ;
+----------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off div -c div
quartus_fit --read_settings_files=off --write_settings_files=off div -c div
quartus_asm --read_settings_files=off --write_settings_files=off div -c div
quartus_tan --read_settings_files=off --write_settings_files=off div -c div --timing_analysis_only