div.fit.summary

FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。

Fitter Status : Successful - Fri Oct 20 16:18:08 2006
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : div
Top-level Entity Name : div
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Final
Total logic elements : 18 / 5,980 ( < 1 % )
Total pins : 22 / 173 ( 13 % )
Total virtual pins : 0
Total memory bits : 0 / 92,160 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )