div.fit.eqn

FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。

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--A1L1 is LessThan~176 at LC_X12_Y20_N9
--operation mode is normal

A1L1 = !a[1] & b[0];


--A1L2 is LessThan~177 at LC_X13_Y20_N5
--operation mode is normal

A1L2 = b[2] # A1L1 # b[1] & !a[2];


--A1L3 is LessThan~178 at LC_X12_Y20_N0
--operation mode is normal

A1L3 = b[2] # b[1] # !a[2] & b[0];


--A1L21 is c_tmp[0]~454 at LC_X12_Y20_N1
--operation mode is normal

A1L21 = a[2] & (a[0] # !b[2] & b[1]) # !a[2] & !b[2] & (a[0]);


--A1L22 is c_tmp[0]~455 at LC_X12_Y20_N5
--operation mode is normal

A1L22 = b[2] & (b[1] $ a[2]) # !b[2] & b[1] & a[2];


--A1L23 is c_tmp[0]~456 at LC_X12_Y20_N8
--operation mode is normal

A1L23 = A1L21 & (b[1]) # !A1L21 & (A1L22 & !b[1] & b[0] # !A1L22 & b[1] & !b[0]);


--A1L24 is c_tmp[0]~457 at LC_X12_Y20_N6
--operation mode is normal

A1L24 = b[0] & A1L21 & (A1L22 # !b[1]) # !b[0] & (A1L22 & !b[1]);


--A1L25 is c_tmp[0]~458 at LC_X12_Y20_N7
--operation mode is normal

A1L25 = A1L24 $ (!a[1] # !A1L23);


--A1L37 is reduce_or~739 at LC_X13_Y20_N2
--operation mode is normal

A1L37 = A1L3 & (A1L2) # !A1L3 & !A1L25 & !A1L2;


--A1L38 is reduce_or~740 at LC_X13_Y20_N3
--operation mode is normal

A1L38 = A1L25 & (A1L2 # !A1L3) # !A1L25 & !A1L3 & A1L2;


--A1L44 is rtl~14 at LC_X13_Y20_N9
--operation mode is normal

A1L44 = !b[2] & (!b[1]);


--A1L39 is reduce_or~741 at LC_X13_Y20_N6
--operation mode is normal

A1L39 = A1L44 & A1L1 & a[2] # !A1L25;


--A1L40 is reduce_or~742 at LC_X13_Y20_N4
--operation mode is normal

A1L40 = A1L25 & !A1L3 & A1L2 # !A1L25 & (A1L3 $ !A1L2);


--A1L41 is reduce_or~743 at LC_X13_Y20_N8
--operation mode is normal

A1L41 = A1L3 # A1L25 $ !A1L2;


--A1L42 is reduce_or~744 at LC_X13_Y20_N7
--operation mode is normal

A1L42 = A1L2 & (A1L25 $ A1L3);


--A1L35 is reduce_or~735 at LC_X12_Y20_N4
--operation mode is normal

A1L35 = !b[1] & (!a[0] & a[1] # !b[0]);


--A1L36 is reduce_or~736 at LC_X12_Y20_N2
--operation mode is normal

A1L36 = b[0] $ (!a[1] # !b[1]);


--A1L43 is reduce_or~745 at LC_X12_Y20_N3
--operation mode is normal

A1L43 = !b[2] & (a[2] & (A1L36) # !a[2] & A1L35);


--b[0] is b[0] at PIN_236
--operation mode is input

b[0] = INPUT();


--a[1] is a[1] at PIN_234
--operation mode is input

a[1] = INPUT();


--b[2] is b[2] at PIN_238
--operation mode is input

b[2] = INPUT();


--b[1] is b[1] at PIN_237
--operation mode is input

b[1] = INPUT();


--a[2] is a[2] at PIN_235
--operation mode is input

a[2] = INPUT();


--a[0] is a[0] at PIN_233
--operation mode is input

a[0] = INPUT();


--c[0] is c[0] at PIN_194
--operation mode is output

c[0] = OUTPUT(VCC);


--c[1] is c[1] at PIN_197
--operation mode is output

c[1] = OUTPUT(A1L37);


--c[2] is c[2] at PIN_200
--operation mode is output

c[2] = OUTPUT(!A1L38);


--c[3] is c[3] at PIN_201
--operation mode is output

c[3] = OUTPUT(A1L39);


--c[4] is c[4] at PIN_202
--operation mode is output

c[4] = OUTPUT(A1L40);


--c[5] is c[5] at PIN_203
--operation mode is output

c[5] = OUTPUT(A1L43);


--c[6] is c[6] at PIN_214
--operation mode is output

c[6] = OUTPUT(!A1L41);


--c[7] is c[7] at PIN_215
--operation mode is output

c[7] = OUTPUT(A1L42);


--en[0] is en[0] at PIN_193
--operation mode is output

en[0] = OUTPUT(GND);


--en[1] is en[1] at PIN_188
--operation mode is output

en[1] = OUTPUT(VCC);


--en[2] is en[2] at PIN_187
--operation mode is output

en[2] = OUTPUT(VCC);


--en[3] is en[3] at PIN_186
--operation mode is output

en[3] = OUTPUT(VCC);


--en[4] is en[4] at PIN_185
--operation mode is output

en[4] = OUTPUT(VCC);


--en[5] is en[5] at PIN_184
--operation mode is output

en[5] = OUTPUT(VCC);


--en[6] is en[6] at PIN_183
--operation mode is output

en[6] = OUTPUT(VCC);


--en[7] is en[7] at PIN_182
--operation mode is output

en[7] = OUTPUT(VCC);