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📄 cmp.fit.eqn

📁 FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。
💻 EQN
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L1 is LessThan~349 at LC_X4_Y20_N4
--operation mode is normal

A1L1 = a[1] & b[0] & b[1] & !a[0] # !a[1] & (b[1] # b[0] & !a[0]);


--A1L2 is LessThan~350 at LC_X4_Y20_N5
--operation mode is normal

A1L2 = a[2] & A1L1 & b[2] # !a[2] & (A1L1 # b[2]);


--A1L3 is LessThan~351 at LC_X4_Y20_N2
--operation mode is normal

A1L3 = b[3] & (A1L2 # !a[3]) # !b[3] & !a[3] & (A1L2);


--b[3] is b[3] at PIN_240
--operation mode is input

b[3] = INPUT();


--a[3] is a[3] at PIN_236
--operation mode is input

a[3] = INPUT();


--b[2] is b[2] at PIN_239
--operation mode is input

b[2] = INPUT();


--a[2] is a[2] at PIN_235
--operation mode is input

a[2] = INPUT();


--b[1] is b[1] at PIN_238
--operation mode is input

b[1] = INPUT();


--b[0] is b[0] at PIN_237
--operation mode is input

b[0] = INPUT();


--a[0] is a[0] at PIN_233
--operation mode is input

a[0] = INPUT();


--a[1] is a[1] at PIN_234
--operation mode is input

a[1] = INPUT();


--c[0] is c[0] at PIN_194
--operation mode is output

c[0] = OUTPUT(VCC);


--c[1] is c[1] at PIN_197
--operation mode is output

c[1] = OUTPUT(VCC);


--c[2] is c[2] at PIN_200
--operation mode is output

c[2] = OUTPUT(!A1L3);


--c[3] is c[3] at PIN_201
--operation mode is output

c[3] = OUTPUT(!A1L3);


--c[4] is c[4] at PIN_202
--operation mode is output

c[4] = OUTPUT(!A1L3);


--c[5] is c[5] at PIN_203
--operation mode is output

c[5] = OUTPUT(GND);


--c[6] is c[6] at PIN_214
--operation mode is output

c[6] = OUTPUT(GND);


--c[7] is c[7] at PIN_215
--operation mode is output

c[7] = OUTPUT(!A1L3);


--en[0] is en[0] at PIN_193
--operation mode is output

en[0] = OUTPUT(GND);


--en[1] is en[1] at PIN_188
--operation mode is output

en[1] = OUTPUT(VCC);


--en[2] is en[2] at PIN_187
--operation mode is output

en[2] = OUTPUT(VCC);


--en[3] is en[3] at PIN_186
--operation mode is output

en[3] = OUTPUT(VCC);


--en[4] is en[4] at PIN_185
--operation mode is output

en[4] = OUTPUT(VCC);


--en[5] is en[5] at PIN_184
--operation mode is output

en[5] = OUTPUT(VCC);


--en[6] is en[6] at PIN_183
--operation mode is output

en[6] = OUTPUT(VCC);


--en[7] is en[7] at PIN_182
--operation mode is output

en[7] = OUTPUT(VCC);
















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